code vhdl

[Ayoub]

Hi guys !


Can you help me correcting this code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cdma_testbipo is

port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic ;
odata: out std_logic ;
type Re is array(0 to 3)of integer range 0 to 15;
signal CD: Re ;
isis ut integer range 0 to 3 ;
S ut integer range -8 to 7 );
end entity ;

architecture beh of cdma_testbipo is

type RAM is array (0 to 3) of integer range -8 to 7;
signal i :integer range 0 to 3 ;
signal code : RAM;
signal idata :std_logic ;

begin

code(0)<=CD(15 downto 12);
code(1)<=CD(11 downto 8) ;
code(2)<=CD(7 downto 4) ;
code(3)<=CD(3 downto 0) ;
bpsk rocess(clk,rst)
begin
if(rst='1')then
i<= 0;
else
if(clk'event and clk='1')then

i<=i+1 ;
if(idata='0') then
s<=-code(i);
else
s<=code(i);
end if;

if(i=3) then
idata<=data;
end if;

end if ;
end if ;
end process ;
isis<=i;

odata<=idata ;
end architecture ;


I think my problem is near :" type Re is array(0 to 3)of integer range 0 to 15;
signal CD: Re ; ""

Error : ""Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" ""

Thank you :!

 

[Rob Gaddi]

Hi guys !


Can you help me correcting this code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cdma_testbipo is

port (
clk : in std_logic ;
rst : in std_logic ;
data: in std_logic ;
odata: out std_logic ;
type Re is array(0 to 3)of integer range 0 to 15;
signal CD: Re ;
isis ut integer range 0 to 3 ;
S ut integer range -8 to 7 );
end entity ;

architecture beh of cdma_testbipo is

type RAM is array (0 to 3) of integer range -8 to 7;
signal i :integer range 0 to 3 ;
signal code : RAM;
signal idata :std_logic ;

begin

code(0)<=CD(15 downto 12);
code(1)<=CD(11 downto 8) ;
code(2)<=CD(7 downto 4) ;
code(3)<=CD(3 downto 0) ;
bpsk rocess(clk,rst)
begin
if(rst='1')then
i<= 0;
else
if(clk'event and clk='1')then

i<=i+1 ;
if(idata='0') then
s<=-code(i);
else
s<=code(i);
end if;

if(i=3) then
idata<=data;
end if;

end if ;
end if ;
end process ;
isis<=i;

odata<=idata ;
end architecture ;


I think my problem is near :" type Re is array(0 to 3)of integer range 0 to 15;
signal CD: Re ; ""

Error : ""Error (10500): VHDL syntax error at cdma_testbipo.vhd(12) near text "type"; expecting an identifier ("type" is a reserved keyword), or "constant", or "file", or "signal", or "variable" ""

Thank you :!

A) You can't declare a type inside of a port list. A type that you
need to in in a port list should be in a separate package.

B) "clk'event and clk == '1'" is ancient style. You weren't even born
yet when they added the rising_edge() function to the standard
library. For the love of god use it.

C) Whatever it is you're trying to do with "CD" and "code" is so tangled
and full of misunderstandings of the language that I can't even begin
to guess what it is you think it SHOULD accomplish. But an unresolved
signal, such as an integer, can only have one driver. It can be in a
process, or in a freefloating statement (which is just a shorthand for
a process), but you can't do it in both.

D) Pertinent to C, your code is entirely devoid of documentation.
Therefore, not only won't you know what you're doing, but no one will
know what you're doing.