hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity riconoscitoremealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end riconoscitoremealy;
architecture Behavioral of riconoscitoremealy is
type state is (st0, st1, st2);
signal present_state, next_state : state;
begin
syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0';
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when St1 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when St2 =>
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =>
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity riconoscitoremealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end riconoscitoremealy;
architecture Behavioral of riconoscitoremealy is
type state is (st0, st1, st2);
signal present_state, next_state : state;
begin
syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;
next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0';
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when St1 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when St2 =>
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =>
next_state <= st0;
dout <= '0';
end case;
end process;
end Behavioral;
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