Problem With Mealy Sequence Detector


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Sep 1, 2017
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hello, i need help with VHDL sequence detector (101) project. I wrote VHDL file but output dout goes to 1 when machine is on "Next state" and not on "Present state". In other words machine gives output 1 on the falling edge of clock and not rising edge. anyone can help me? thanks

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity riconoscitoremealy is
Port ( clk : in STD_LOGIC;
din : in STD_LOGIC;
rst : in STD_LOGIC;
dout : out STD_LOGIC);
end riconoscitoremealy;

architecture Behavioral of riconoscitoremealy is
type state is (st0, st1, st2);
signal present_state, next_state : state;
begin

syncronous_process : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
present_state <= st0;
else
present_state <= next_state;
end if;
end if;
end process;

next_state_and_output_decoder : process(present_state, din)
begin
dout <= '0';
case (present_state) is
when st0 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st0;
dout <= '0';
end if;
when St1 =>
if (din = '1') then
next_state <= st1;
dout <= '0';
else
next_state <= st2;
dout <= '0';
end if;
when St2 =>
if (din = '1') then
next_state <= st1;
dout <= '1';
else
next_state <= st0;
dout <= '0';
end if;
when others =>
next_state <= st0;
dout <= '0';
end case;
end process;

end Behavioral;
Schermata_2017-09-01_alle_20.39.59.png
 
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Cor

Joined
Oct 13, 2017
Messages
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Hi Armand,

The data does not change on the falling clock edge; it changes due to the change on din.
If you would shift din in time; you would see this.
You have created a mealy state machine, where the output depends on the current state and the input. Therefore the output changes on either state transition or on input change...
If this is undesired, use a moore state machine, where the output dout only depends on the present state.

Regards,

Cor
 

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