Parallel load register 4 bit without using instantiation

Discussion in 'VHDL' started by chirag.nitb, May 28, 2014.

  1. chirag.nitb

    chirag.nitb Guest

    Need to design a 4 bit register with parallel loading using D flip flop . Iwrote the following code in xilinx but the simulation shows an undefined state and the code does not work if the initial values of the out put are set to zero . Please help correcting the code


    Here is the code

    ----------------------------------------------------------------------------------
    -- Company:
    -- Engineer:
    --
    -- Create Date: 14:06:13 05/27/2014
    -- Design Name:
    -- Module Name: code - Behavioral
    -- Project Name:
    -- Target Devices:
    -- Tool versions:
    -- Description:
    --
    -- Dependencies:
    --
    -- Revision:
    -- Revision 0.01 - File Created
    -- Additional Comments:
    --
    ----------------------------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    ---- Uncomment the following library declaration if instantiating
    ---- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity code is
    Port ( din : in STD_LOGIC_VECTOR (3 downto 0);
    dout :inout STD_LOGIC_VECTOR (3 downto 0):="0000";
    rd,clk,rst : in STD_LOGIC);
    end code;

    architecture registerdesign of code is
    signal wr: STD_LOGIC;
    signal OPA_0, OPA_1, OPA_2, OPA_3: STD_LOGIC;
    signal OPB_0, OPB_1, OPB_2, OPB_3: STD_LOGIC;
    signal FOP_0, FOP_1, FOP_2, FOP_3: STD_LOGIC;
    begin
    wr <= not(rd);
    OPA_0 <= rd and dout(0);
    OPA_1 <= rd and dout(1);
    OPA_2 <= rd and dout(2);
    OPA_3 <= rd and dout(3);

    OPB_0 <= wr and din(0);
    OPB_1 <= wr and din(1);
    OPB_2 <= wr and din(2);
    OPB_3 <= wr and din(3);

    FOP_0 <= OPA_0 or OPB_0;
    FOP_1 <= OPA_1 or OPB_1;
    FOP_2 <= OPA_2 or OPB_2;
    FOP_3 <= OPA_3 or OPB_3;

    process(clk,rst)
    begin
    if (rst='1')then
    dout <="0000";
    else
    if(clk'event and clk='1')then
    dout(0)<= FOP_0;
    dout(1)<= FOP_1;
    dout(2)<= FOP_2;
    dout(3)<= FOP_3;
    end if;
    end if;
    end process;

    end registerdesign;
     
    chirag.nitb, May 28, 2014
    #1
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  2. chirag.nitb

    rickman Guest

    lol, the -- at the beginning of a line in your code made the newsreader
    think it was the start of the signature.

    Your code will only reset the FFs if rst is equal to '1'. Do you set
    rst = '1' in your simulation?

    I don't see anything wrong with the code for the register. I would
    recommend that you use rising_edge(clk) rather than the clk'event, etc.
    but that won't cause a failure.

    Also, the use of these libraries is *not* recommended...

    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    Use numeric_std instead.

    If you want to know more about these recommendations, do some google
    searches and come back if you still have questions.
     
    rickman, May 28, 2014
    #2
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