FIFO not discarding data

[ts.communicate]

Hi all,

I am new to vhdl and fpga design however I work on a design targeting
Xilinx Virtex-5 and use Xilinx ISE 9.2 as well as 3L's Diamond
software.
We use FPGA for signal processing so I have several tasks and finally
a FIFO that outputs some parameters (7x32bit) through PCI to the host
PC.

The project was working but we needed to change the FIFO to have a
xilinx IP core (from core generator) with 224 bit width(7x32bit).
the aim of the implementation is to discard old data when the FIFO is
getting full in order to have always fresh data, but this does not
happen and the FIFO gets full and does not discard data as it should.
This is the source code. any help is appreciated.
--------------
-- This task is a FIFO
-- It is used to store continuous data flow as the host can not read
at the processing rate
-- FIFO is generated by coregen, Fall through type

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library Smt;
use Smt.Smt_pkg.all;

entity fifo_capture_1_1 is
port (
-- @Diamond3L Begin@
-- Do not alter the contents of the block between the begin and
end tags.
x_chan_in_0 : IN X_chan_t; --port not named
y_chan_in_0 : OUT Y_chan_t; --port not named
x_chan_in_1 : IN X_chan_t; --port not named
y_chan_in_1 : OUT Y_chan_t; --port not named
x_chan_out_0 : OUT X_chan_t; --port not named
y_chan_out_0 : IN Y_chan_t; --port not named
-- @Diamond3L End@

-- The following signals are always required for a task
clk : IN std_logic;
rst : IN std_logic;
ce : IN std_logic;
ce_clr : IN std_logic
-- Do not add any ports after this point
);
end fifo_capture_1_1;

architecture arch of fifo_capture_1_1 is

component fifo_generator_v4_2_1k_224_b
port (
din: IN std_logic_VECTOR(223 downto 0);
prog_full_thresh_assert: IN std_logic_VECTOR(6 downto 0);
prog_full_thresh_negate: IN std_logic_VECTOR(6 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_empty: OUT std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(223 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
prog_full: OUT std_logic);
end component;

signal din: std_logic_VECTOR(223 downto 0);
signal din_temp: std_logic_VECTOR(223 downto 0);
signal prog_full_thresh_assert: std_logic_VECTOR(6 downto 0);
signal prog_full_thresh_negate: std_logic_VECTOR(6 downto 0);
signal rd_clk: std_logic;
signal fifo_out_read: std_logic;
signal restart: std_logic;
signal wr_clk: std_logic;
signal wr_en: std_logic;
signal fifo_dout: std_logic_VECTOR(223 downto 0);
signal empty: std_logic;
signal full: std_logic;
signal prog_full: std_logic;

signal word_in: std_logic_VECTOR(223 downto 0); --input to FIFO
signal word_out: std_logic_VECTOR(223 downto 0); --out from FIFO
signal idx: std_logic_vector(2 downto 0) :=(others=>'0'); --count
input data
signal outCounter: std_logic_vector(2 downto 0) :=(others=>'0'); --
count output data
signal dout: std_logic_vector(31 downto 0); --output to host
signal write_out : std_logic := '0';
Signal packet : std_logic := '0';
Signal almost_empty : std_logic;
Signal almost_full : std_logic;

begin
prog_full_thresh_assert <= conv_std_logic_vector(100,
prog_full_thresh_assert'length);
prog_full_thresh_negate <= conv_std_logic_vector(99,
prog_full_thresh_negate'length);

-- Reset port always ready
y_chan_in_1.ready <= '1';
restart <= rst or x_chan_in_1.write;

-- FIFO accepts data when not full
y_chan_in_0.ready <= not full;

-- Output to host
x_chan_out_0.write <= write_out;
x_chan_out_0.data <= x"00000000"&dout;
x_chan_out_0.validwords <= c_32BITS_DATA;

-----build word and write to FIFO (width 224 bit) ---
p_build_wordrocess (clk,restart)
begin
if restart='1' then
word_in <= (others=>'0');
wr_en <= '0';
elsif (clk'event and clk = '1') then
if( x_chan_in_0.write = '1') then
case conv_integer(x_chan_in_0.data(39 downto 32)) is --case
conv_integer(idx) is--
when 0 =>
word_in(223 downto 192) <= x_chan_in_0.data(31 downto 0);--ext
("0", 32-idx'length) & idx;--
wr_en <= '0';
when 1 =>
word_in(191 downto 160) <= x_chan_in_0.data(31 downto 0);--
conv_std_logic_vector(1,32);-- x_chan_in_0.data(31 downto 0);
wr_en <= '0';
when 2 =>
word_in(159 downto 128) <= x_chan_in_0.data(31 downto 0);--
conv_std_logic_vector(2,32);--x_chan_in_0.data(31 downto 0);
wr_en <= '0';
when 3 =>
word_in(127 downto 96) <=x_chan_in_0.data(31 downto 0);--
conv_std_logic_vector(3,32);-- x_chan_in_0.data(31 downto 0);
wr_en <= '0';
when 4 =>
word_in(95 downto 64) <=x_chan_in_0.data(31 downto 0);--
conv_std_logic_vector(4,32);-- x_chan_in_0.data(31 downto 0);
wr_en <= '0';
when 5 =>
word_in(63 downto 32) <=x_chan_in_0.data(31 downto 0);--
conv_std_logic_vector(5,32);-- x_chan_in_0.data(31 downto 0);
wr_en <= '0';
when 6 =>
din<= word_in(223 downto 32)&x_chan_in_0.data(31 downto 0);--
conv_std_logic_vector(6,32);--x_chan_in_0.data(31 downto 0);
if( almost_full = '0') then --new entry
wr_en <= '1';
else
wr_en <= '0';
end if;
--wr_en <= '1';
when others =>
word_in <= (others=>'0');
wr_en <= '0';
end case;
else
wr_en <= '0';
end if;
end if;
end process p_build_word;


----------------------------------------------------------------------------
End of pipe in

-----------read the word_out - unpack it and output to host
------------------------------
p_read_fiforocess (clk, restart)
begin
if restart='1' then
outCounter <= (others=>'0');
write_out <= '0';
word_out <= (others =>'0');
fifo_out_read <= '0';
elsif (clk'event and clk = '1') then
if( prog_full = '1' ) then ---when prog_full is set. Reading
until deasserted
fifo_out_read <= '1';
write_out <= '0';
elsif( almost_empty= '0' and y_chan_out_0.ready = '1') then
case conv_integer(outCounter) is
when 0 =>
fifo_out_read <= '1';
word_out <= fifo_dout;
dout <= fifo_dout(223 downto 192);
write_out <= '1';
outCounter <= conv_std_logic_vector(1,outCounter'length);
when 1 =>
fifo_out_read <= '0';
dout <= word_out(191 downto 160);
write_out <= '1';
outCounter <= conv_std_logic_vector(2,outCounter'length);
when 2 =>
fifo_out_read <= '0';
dout <= word_out(159 downto 128);
write_out <= '1';
outCounter <= conv_std_logic_vector(3,outCounter'length);
when 3 =>
fifo_out_read <= '0';
dout <= word_out(127 downto 96);
write_out <= '1';
outCounter <= conv_std_logic_vector(4,outCounter'length);
when 4 =>
fifo_out_read <= '0';
dout <= word_out(95 downto 64);
write_out <= '1';
outCounter <= conv_std_logic_vector(5,outCounter'length);
when 5 =>
fifo_out_read <= '0';
dout <= word_out(63 downto 32);
write_out <= '1';
outCounter <= conv_std_logic_vector(6,outCounter'length);
when 6 =>
fifo_out_read <= '0';
dout <= word_out(31 downto 0);
write_out <= '1';
outCounter <= conv_std_logic_vector(0,outCounter'length);
when others =>
fifo_out_read <= '0';
write_out <= '0';
dout <= (others=>'0');
outCounter <= (others=>'0');
end case;
else
fifo_out_read <= '0';
write_out <= '0';
dout <= (others=>'0'); ---test
end if;
end if;
end process p_read_fifo;

---------------------------------------------------------------------------
End of pipe out

-- FIFO synchronous but could be used to change clock domain
wr_clk <= clk;
rd_clk <= clk;
----------------------------------
fifo_lifo_128: fifo_generator_v4_2_1k_224_b
port map (
din => din,
prog_full_thresh_assert => prog_full_thresh_assert,
prog_full_thresh_negate => prog_full_thresh_negate,
rd_clk => rd_clk,
rd_en => fifo_out_read,
rst => restart,
wr_clk => wr_clk,
wr_en => wr_en,
almost_empty => almost_empty,
almost_full => almost_full,
dout => fifo_dout,
empty => empty,
full => full,
prog_full => prog_full);


end arch;


thanks

 

[ts.communicate]

Especially
not when you've used idiot sociopathic tab characters
for indenting.

How hard can this be? A FIFO is, let's try to remember
here, FIRST-IN FIRST-OUT.

ouaouu !! you must be very clever!! I am impressed..

 

[Tricky]

ouaouu !! you must be very clever!! I am impressed..

As am I. Jonathan is a very clever man.

From what I managed to see in your splurged out code, you seem to
write into the FIFO once every 6 valid inputs, storing the next 32
bits of the 224 bit word at the same time. If the fifo is nearly full,
you read 1 value out. There doesnt seem to be a problem to me.

Now if you actually told us how the rest of the system worked worked,
and how old "old" data actually is, I think we could be of more help.
Telling us that its just not working as YOU expect, doesnt help us. I
recon it works fine as written in the code. We have no idea how often
the Y_chan_out_0 is ready.

Like Jonathan said, if you dont need the data in the fifo any more,
you have to throw it away, which you appear to do already.

We dont like working your code out for you. Please run it through a
good testbench in your favorite simulator first before asking a better
phrased q.

 

[ts.communicate]

We dont like working your code out for you. Please run it through a

good testbench in your favorite simulator first before asking a better
phrased q.

thanks for replying. I didn't ask from you to work out the code. I was
just upset by the tone of the reply.
Anyway I though that it was something specific to xilinx fifo ip core
but this is not the case.
I have continuous flow of data and reading from the host PC. I have to
discard the old data and try to read from the PC as much as I can from
the fresh data because the host can not read at the processing rate.
I'll try to post extra data when available.

 

[Mike Treseler]

ouaouu !! you must be very clever!! I am impressed..

http://www.catb.org/~esr/faqs/smart-questions.html