Is my port map syntax right???? i am not able to find the proper guidance for the error in any book

Discussion in 'VHDL' started by keerthi_raj, Mar 19, 2016.

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is the port map syntax right

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  2. yes

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  1. keerthi_raj

    keerthi_raj

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    The code was developed for a project in which the port maps have a expression...well i couldn't find any brief explanation about this in any of the text books...so if anyone can help me with the error in the code shown below,

    Code (Text):
    library IEEE;
    use IEEE.std_logic_1164.all;
    useIEEE.std_logic_unsigned.all;
    entity count is
    port(clock,csb,ldb:instd_logic;
    reset: in std_logic;
    drive: out std_logic_vector(8 downto 0);
    code: out std_logic_vector(7 downto 0);
    scan: in std_logic_vector(4 downto 0);
    cd: out std_logic;
    rptb: inoutstd_logic;
    dab: inoutstd_logic);
    end count;
    architecturecount_arch of count is
    component counter1
    port(clk,rst,stop,ldb,csb: in std_logic;
    q:inout std_logic_vector(2 downto 0));
    end component;
    component counter2
    port(clk1,rst1,stop1,ldb1,csb1: in std_logic;
    qb:inoutstd_logic_vector(4 downto 0));
    end component;
    component latch1
    port(enable,rst2,data: in std_logic;
    dout:outstd_logic);
    end component;
    component decoder35
    port(sel: in std_logic_vector(2 downto 0);
    decout:outstd_logic_vector(4 downto 0));
    end component;
    component dff1
    port(ck,din,cs1,rptb: in std_logic;
    qdb:outstd_logic);
    end component;
    componentlut
    port(sel1: in std_logic_vector(7 downto 0);
    rst4: in std_logic;
    drive1:outstd_logic_vector(8 downto 0));
    end component;
    componentdebounce
    port(clk,rst3,kd1: in std_logic;
    cd:outstd_logic);
    end component;
    componentlowdis
    port(rst10,ldb,sig2: in std_logic;
    dab1:outstd_logic);
    end component;
    signal x:std_logic_vector(2 downto 0);
    signala,y: std_logic_vector(4 downto 0);
    signal sig1,b,c,d,n1,n2,n3,n4,n5: std_logic;
    signal q2:std_logic_vector(7 downto 0);
    signalkd:std_logic;
    begin
    kd<=not(n1 and n2 and n3 and n4 and n5);
    u1:counter1
    port map(clock,reset,kd,ldb,csb,x);
    u2:decoder35
    port map(x(2),reset,kd,ldb,csb,y);
    u3:decoder35
    port map(x,a);
    u4:latch1
    port map(a(0),scan(0),reset,n1);
    u5:latch1
    port map(a(1),scan(1),reset,n2);
    u6:latch1
    port map(a(2),scan(2),reset,n3);
    u7:latch1
    port map(a(3),scan(3),reset,n4);
    u8:latch1
    port map(a(4),scan(4),reset,n5);
    u9:lut
    port map((y&x),reset,drive);         <<this is the line where i'm finding the error
    u10:dff1
    port map(a(clock,kd,csb,rptb,sig1);
    u11:debounce
    port map(reset,clock,kd,cd);
    u12:lowdis
    port map(reset,ldb,sig1,dab);
    process(csb,x,y,dab)
    begin
    ifcsb=’0’ then
    q2<=y & x;
    else
    q2(7)<=’1’;
    end if;
    end process;
    process(kd,dab,reset,ldb,clock)
    begin
    if(reset=’1’) then
    rptb<=’1’;
    elsif(kd=’1’ and ldb=’0’) then
    if(dab=’0’) then
    rptb<=’1’;
    elsif(dab=’1’) then
    rptb<=’0’;
    end if;
    elsif(kd=’0’) then
    if(ldb’event and ldb=’1’) then
    if(clock’event and clock=’1’) then
    rptb<=’1’;
    end if;
    end if;
    end if;
    end process;
    process(q2)
    begin
    case q2 is
    when “00000000”=>code<=”00110000”;
    when “00000001”=>code<=”00110010”;
    when “00000010”=>code<=”00110011”;
    when “00000011”=>code<=”00110101”;
    when “00000100”=>code<=”00110111”;
    when “00001000”=>code<=”00111000”;
    when “00001001”=>code<=”00111010”;
    when “00001010”=>code<=”00111011”;
    when “00001011”=>code<=”00101101”;
    when “00001100”=>code<=”00101111”;
    when “00010000”=>code<=”01000000”;
    when “00010001”=>code<=”00000010”;
    when “00010010”=>code<=”00000011”;
    when “00010011”=>code<=”00000001”;
    when “00010100”=>code<=”00000111”;
    when “00011000”=>code<=”00001000”;
    when “00011001”=>code<=”00001010”;
    when “00000010”=>code<=”00000011”;
    when “00000011”=>code<=”00000001”;
    when “00000100”=>code<=”00001111”;
    when “00100000”=>code<=”00000000”;
    when “00100001”=>code<=”00000010”;
    when “00000010”=>code<=”01010011”;
    when “00100011”=>code<=”01010101”;
    when “00100100”=>code<=”01010111”;
    when “00101000”=>code<=”01011000”;
    when “00101001”=>code<=”01011010”;
    when “00101010”=>code<=”01011011”;
    when “00101011”=>code<=”01011101”;
    when “00101100”=>code<=”01011111”;
    when “00110000”=>code<=”00100000”;
    when “00110001”=>code<=”00001010”;
    when “00110010”=>code<=”00011011”;
    when “00110011”=>code<=”00001101”;
    when “00110100”=>code<=”01111111”;
    when “00111000”=>code<=”10000000”;
    when “00111001”=>code<=”10000010”;
    when “00111010”=>code<=”10000011”;
    when “00111011”=>code<=”10000101”;
    when “00111100”=>code<=”10000111”;
    when “01000000”=>code<=”10001000”;
    when “01000001”=>code<=”10001010”;
    when “01000010”=>code<=”10001011”;
    when “01000011”=>code<=”10001101”;
    when “01000100”=>code<=”10001111”;
    when others=>code<=”ZZZZZZZZ”;
    end case;
    end process;
    endcount_arch;
     
    please help me out...!!! the tool used is xilinx 10.1
     
    keerthi_raj, Mar 19, 2016
    #1
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