error: (infix expression) for formal "din" is not a globally static expression


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hi, this is a code i wrote for a barrel shift register:

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

Entity BARREL is Port(
CLK: in std_logic; -- CLOCK
RST: in std_logic; -- RESET
DIN: in std_logic_vector(7 downto 0); -- PARALLEL DATA INPUT
ROT_SEL: in std_logic_vector(2 downto 0); -- NUM OF BITS ROTATE SELECT
LR_SEL: in std_logic; -- SHIFT DIRECTION SELECT '1'-LEFT/'0'-RIGHT
SOUT: out std_logic_vector(7 downto 0)); -- PARALLEL OUTPUT
End Entity;

Architecture BEHAVE of BARREL is
component myMUX is Port(
CLK: in std_logic;
DIN: in std_logic_vector(7 downto 0); -- PARALLEL DATA INPUT
ROT_SEL: in std_logic_vector(2 downto 0); -- NUM OF BITS ROTATE SELECT
SOUT: out std_logic); -- PARALLEL OUTPUT
End component;


Signal INNER_DATA: std_logic_vector(15 downto 0);
Signal TURN: std_logic_vector(2 downto 0); -- NUM OF BITS ROTATE SELECT

Begin
G: for i in 0 to 7 generate
m1: myMUX port map (CLK,INNER_DATA((I+7) downto (I+1))&DIN(I),TURN,INNER_DATA(i));
end GENERATE;

Process (RST,CLK)
Begin
if rising_edge(CLK) Then -- SYNCHRONOUS OPERATIONS OF SYSTEM
Case LR_SEL is
When '0'=> TURN<= ROT_SEL;
When '1'=> TURN<= 8-ROT_SEL;
When others => NULL;
End case;
End if;
End process;
INNER_DATA(15 downto 8) <= INNER_DATA(7 downto 0);
with RST select
SOUT <= (others=>'0') when '1',
INNER_DATA(7 downto 0) when others;
End BEHAVE;
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the file was compiled and programed into a cyclone ii altera student kit and performed like clock work....but at home when i tried to compile it with MODELSIM...it gave me this error notice:

# ** Error: BARREL.vhd(28): Actual (infix expression) for formal "din" is not a globally static expression.

i undestand it's regarding to the input vector i'm sending in the port map of the myMUX component but i can't understand what's wrong...after all it worked...

please help,
tomer.
 
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