Xilinx ISE, expression not globally static inside generic map

Discussion in 'VHDL' started by Zo Ki, Nov 22, 2016.

  1. Zo Ki

    Zo Ki

    Nov 22, 2016
    Likes Received:

    Is this allowed inside Xilinx ISE : generic map (record1.field1'length) ??

    Previously I have defined record:

    type test_record is record
    field1 : std_logic_vector(31 downto 0);
    field2 : std_logic_vector(31 downto 0);
    end record;

    constant record1 : test_record := ((others => '0'),(others => '0'));

    I get this error message:

    The actual value (Attribute name) associated with a generic must be a globally static expression

    Thanks in advance :)
    Zo Ki, Nov 22, 2016
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