Compiling error... not sure how to address the errors

Discussion in 'VHDL' started by Zak Asaad, Apr 22, 2013.

  1. Zak Asaad

    Zak Asaad Guest

    Hi, Im new here and fairly new to vhdl. Im designing a simple register bank.. My main issue is handling the integers in a case statement. I think I am missing something, but I don't know what. Im using ModelSim to code. Here is my code. You can paste it in a program and try to compile to see the error I am getting, but I am going to post the errors, in case you dont have the program. Thanks:

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;

    entity RegBank16x8 IS
    port( clk : IN std_logic;
    writeEnable : IN std_logic;
    w_bk_aluop_reg : IN std_logic_vector (7 downto 0);
    rdx_decoder_reg , rdy_decoder_reg : IN std_logic_vector (3 downto 0);
    rx_reg_alu, ry_reg_mux : OUT std_logic_vector(7 downto 0);
    wr_sp_e_reg_scratchpad : IN std_logic

    );

    end RegBank16x8;

    architecture RegisterBank of RegBank16x8 is

    --type register_array is array(0 to 15) of std_logic_vector(7 downto 0);
    --signal reg : register_array;

    signal reg0 : std_logic_vector(7 downto 0) := "01111000";
    signal reg1 : std_logic_vector(7 downto 0) := "00010100";
    signal reg2 : std_logic_vector(7 downto 0) := "00010000";
    signal reg3 : std_logic_vector(7 downto 0) := "00000011";
    signal reg4 : std_logic_vector(7 downto 0) := "00000000";
    signal reg5 : std_logic_vector(7 downto 0) := "01111110";
    signal reg6 : std_logic_vector(7 downto 0) := "10000001";
    signal reg7 : std_logic_vector(7 downto 0) := "00111000";
    signal reg8 : std_logic_vector(7 downto 0) := "10000000";
    signal reg9 : std_logic_vector(7 downto 0) := "11111111";
    signal reg10 : std_logic_vector(7 downto 0) := "00111000";
    signal reg11 : std_logic_vector(7 downto 0) := "00000000";
    signal reg12 : std_logic_vector(7 downto 0) := "01010010";
    signal reg13 : std_logic_vector(7 downto 0) := "00100100";
    signal reg14 : std_logic_vector(7 downto 0) := "00000001";
    signal reg15 : std_logic_vector(7 downto 0) := "01111111";




    begin

    variable temp_rxCount : range Integer 0 to 16;
    variable temp_ryCount : range Integer 1 to 17;

    variable rxCount : range Integer 0 to 16;
    variable ryCount : range Integer 1 to 17;

    ---- reg0 <= "00000000";
    -- reg1 <= "00011010";
    -- reg2 <= "00100101";
    -- reg3 <= "00100010";
    -- reg4 <= "01011010";
    -- reg5 <= "00000000";
    -- reg6 <= "00000010";
    -- reg7 <= "00010011";
    -- reg8 <= "10000001";
    -- reg9 <= "00001000";
    -- reg10 <= "00000111";
    -- reg11 <= "01010101";
    -- reg12 <= "01100110";
    -- reg13 <= "00000110";
    -- reg14 <= "01111111";
    -- reg15 <= "01111110";


    first: process (clk, writeEnable, rdx_decoder_reg, rdy_decoder_reg, w_bk_aluop_reg)
    begin



    if clk'event and clk='1' then

    if (wr_sp_e_reg_scratchpad = '1') then --if register is enabled to write to scratchpad, execute the following



    case rxCount is
    when 0 => rx_reg_alu <= reg0;
    when 2 => rx_reg_alu <= reg2;
    when 4 => rx_reg_alu <= reg4;
    when 6 => rx_reg_alu <= reg6;
    when 8 => rx_reg_alu <= reg8;
    when 10 => rx_reg_alu <= reg10;
    when 12 => rx_reg_alu <= reg12;
    when 14 => rx_reg_alu <= reg14;
    when others => null;
    end case;

    temp_rxCount := rxCount + 2;
    rxCount := temp_rxCount;


    case ryCount is
    when 1 => ry_reg_mux <= reg1;
    when 3 => ry_reg_mux <= reg3;
    when 5 => ry_reg_mux <= reg5;
    when 7 => ry_reg_mux <= reg7;
    when 9 => ry_reg_mux <= reg9;
    when 11 => ry_reg_mux <= reg11;
    when 13 => ry_reg_mux <= reg13;
    when 15 => ry_reg_mux <= reg15;
    when others => null;
    end case;

    temp_ryCount := ryCount + 2;
    ryCount := temp_ryCount;

    if (rxCount = 16) then
    rxCount := 0;
    end if;
    if (ryCount = 17) then
    ryCount := 1;
    end if;

    else --if register is NOT enabled to write to scratchpad then willcontinue with usual processes

    if (writeEnable='1') then

    case rdx_decoder_reg is
    when "0000" => reg0 <= w_bk_aluop_reg;
    when "0001" => reg1 <= w_bk_aluop_reg;
    when "0010" => reg2 <= w_bk_aluop_reg;
    when "0011" => reg3 <= w_bk_aluop_reg;
    when "0100" => reg4 <= w_bk_aluop_reg;
    when "0101" => reg5 <= w_bk_aluop_reg;
    when "0110" => reg6 <= w_bk_aluop_reg;
    when "0111" => reg7 <= w_bk_aluop_reg;
    when "1000" => reg8 <= w_bk_aluop_reg;
    when "1001" => reg9 <= w_bk_aluop_reg;
    when "1010" => reg10<= w_bk_aluop_reg;
    when "1011" => reg11<= w_bk_aluop_reg;
    when "1100" => reg12<= w_bk_aluop_reg;
    when "1101" => reg13<= w_bk_aluop_reg;
    when "1110" => reg14<= w_bk_aluop_reg;
    when "1111" => reg15<= w_bk_aluop_reg;
    when others => null;
    end case;

    else
    case rdx_decoder_reg is
    when "0000" => rx_reg_alu <= reg0;
    when "0001" => rx_reg_alu <= reg1;
    when "0010" => rx_reg_alu <= reg2;
    when "0011" => rx_reg_alu <= reg3;
    when "0100" => rx_reg_alu <= reg4;
    when "0101" => rx_reg_alu <= reg5;
    when "0110" => rx_reg_alu <= reg6;
    when "0111" => rx_reg_alu <= reg7;
    when "1000" => rx_reg_alu <= reg8;
    when "1001" => rx_reg_alu <= reg9;
    when "1010" => rx_reg_alu <= reg10;
    when "1011" => rx_reg_alu <= reg11;
    when "1100" => rx_reg_alu <= reg12;
    when "1101" => rx_reg_alu <= reg13;
    when "1110" => rx_reg_alu <= reg14;
    when "1111" => rx_reg_alu <= reg15;
    when others => null;
    end case;

    case rdy_decoder_reg is
    when "0000" => ry_reg_mux <= reg0;
    when "0001" => ry_reg_mux <= reg1;
    when "0010" => ry_reg_mux <= reg2;
    when "0011" => ry_reg_mux <= reg3;
    when "0100" => ry_reg_mux <= reg4;
    when "0101" => ry_reg_mux <= reg5;
    when "0110" => ry_reg_mux <= reg6;
    when "0111" => ry_reg_mux <= reg7;
    when "1000" => ry_reg_mux <= reg8;
    when "1001" => ry_reg_mux <= reg9;
    when "1010" => ry_reg_mux <= reg10;
    when "1011" => ry_reg_mux <= reg11;
    when "1100" => ry_reg_mux <= reg12;
    when "1101" => ry_reg_mux <= reg13;
    when "1110" => ry_reg_mux <= reg14;
    when "1111" => ry_reg_mux <= reg15;
    when others => null;
    end case;

    end if;
    end if;
    end if;
    end process first;
    end RegisterBank;


    And here are the errors the code is throwing:

    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(44): near "variable": syntax error
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(79): (vcom-1136) Unknown identifier "rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(80): Enumeration literal '0' is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(81): Enumeration literal '2' is type std.STANDARD.CHARACTER; expecting type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(82): Integer literal 4 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(83): Integer literal 6 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(84): Integer literal 8 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(85): Integer literal 10 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(86): Integer literal 12 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(87): Integer literal 14 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(91): (vcom-1136) Unknown identifier "rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(91): (vcom-1136) Unknown identifier "temp_rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(91): Bad right hand side (infix expression) in variable assignment.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(92): (vcom-1136) Unknown identifier "rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(92): (vcom-1136) Unknown identifier "temp_rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(95): (vcom-1136) Unknown identifier "ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(96): Integer literal 1 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(97): Integer literal 3 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(98): Integer literal 5 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(99): Integer literal 7 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(100): Integer literal 9 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(101): Integer literal 11 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(102): Integer literal 13 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(103): Integer literal 15 is not of type (error).
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(107): (vcom-1136) Unknown identifier "ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(107): (vcom-1136) Unknown identifier "temp_ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(107): Bad right hand side (infix expression) in variable assignment.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(108): (vcom-1136) Unknown identifier "ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(108): (vcom-1136) Unknown identifier "temp_ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(110): (vcom-1136) Unknown identifier "rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(110): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(111): (vcom-1136) Unknown identifier "rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(111): Target type (error) in variable assignment is different from expression type Integer.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(111): (vcom-1136) Unknown identifier "rxCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(113): (vcom-1136) Unknown identifier "ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(113): Type error resolving infix expression "=" as type std.STANDARD.BOOLEAN.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(114): (vcom-1136) Unknown identifier "ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(114): Target type (error) in variable assignment is different from expression type Integer.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(114): (vcom-1136) Unknown identifier "ryCount".
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(186): VHDL Compiler exiting

    I know it looks like a lot of errors but Im sure its a small issue that will get rid of most of the errors. Thanks for looking
     
    Zak Asaad, Apr 22, 2013
    #1
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  2. Zak Asaad

    Zak Asaad Guest

    Oh and the errors are all coming from the first two case statements utilizing the rxCount and ryCount variables inside the cases. The rest of the code after those is ok because the first two case statements are being added to working/compiling code.
     
    Zak Asaad, Apr 22, 2013
    #2
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  3. Zak Asaad

    goouse99 Guest

    Am Montag, 22. April 2013 07:01:27 UTC+2 schrieb Zak Asaad:
    Hi,
    you have missed the very first error on line 44.
    ** Error: /afs/uncc.edu/usr/s/zasaad/linux/Desktop/RISC Project/RegisterBank16x8.vhd(44): near "variable": syntax error

    Variables have to be declared inside a process.

    Have a nice simulation
    Eilert
     
    goouse99, Apr 22, 2013
    #3
  4. Am Montag, 22. April 2013 07:01:27 UTC+2 schrieb Zak Asaad:
    No error, but source of a lot problems. Using this library is in best case outdated since 10 years, as it is despite beeing named ieee no standard and might vary from tool to tool. Please use numeric_std instead.
    This definition is wrong and causes most likely also most following errors.
    1. put in in process
    2. Integer range 0 to 16 (you sure not to use 0 to 15 instead?)


    BTW is there a reason, why you avoid array for the regfile?
    e.g:

    type regfile_t is array 0 to 15 of std_ulogic_vector(7 downto 0)
    use ieee.numeric_std.all;
    signal my_regfile : regfile_t; -- initial signal assignments are dangerous!

    if reset = activelevel then
    my_regfile <= (0 => x"38", 1 => x"14",...)
    elsif rising_edge(Clk) then
    rx_reg_alu <= my_regfile(rx_count);
    ry_reg_alu <= my_regfile(ry_count);
    ...
    if write_enable='1' then
    my_regfile(to_integer(unsigned(rdx_decoder_reg))) <= w_bk_aluop_reg;
    end if;
    ..

    best regards Thomas
     
    Thomas Stanka, Apr 22, 2013
    #4
  5. Zak Asaad

    Andy Guest

    In addition to previously noted problems, some additional suggestions:

    Clocked processes' sensitivity lists should not contain signals other than the clock, and possibly an asynchronous reset, if applicable.

    Use the rising_edge(clk) function instead of clk'event and clk = '1' to detect the clock edge; the function is standard, more robust, and more readable.

    Integer counters don't rollover in simulation. Synthesis optimization will usually implement a rollover counter, but then the behavior of your circuitand your simulation will not agree. If a rollover is desired for integer counters, use "(count + 1) mod 16", where mod's RH argument is a power of two.

    Resetting via initialization is hazardous, and non-portable. Implement a HWreset (either asynchronous or synchronous).

    If your tools support the vhdl-2008 language version, you can use the ieee.numeric_std_unsigned package, which defines arithmetic operations on std_logic_vectors using an unsigned interpretation of the contents. It is similarto std_logic_arith in concept, but is an officially supported IEEE standard package (like numeric_std). It also defines to_integer() and to_slv() conversion functions.

    I strongly agree with the use of arrays for the registers in an applicationsuch as this.

    Andy
     
    Andy, Apr 22, 2013
    #5
  6. Zak Asaad

    Zak Asaad Guest

    this actually help get rid of most of the errors. Thanks man. And also, I found a mistake in my signal declarations for my variable assignments. The "range" comes after the "integer". That was completely foolish on my part. Igot the whole thing working now. Thanks
     
    Zak Asaad, Apr 23, 2013
    #6
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