VHDL program error


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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:24:25 11/03/2014
-- Design Name:
-- Module Name: WIFI_CODE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity WIFI_CODE is
Port ( CLOCK : in STD_LOGIC;
RESET : in STD_LOGIC;
--TRS_EN : out STD_LOGIC;
--CARD_READY : in STD_LOGIC;
DATA_IN: in STD_LOGIC_VECTOR(7 downto 0);
--WLAN_ACT : in STD_LOGIC;
MOSI : inout STD_LOGIC_VECTOR(7 downto 0);
MISO : inout STD_LOGIC_VECTOR(7 downto 0);
SPI_CLK : out STD_LOGIC;
CS : out STD_LOGIC);
end WIFI_CODE;

architecture Behavioral of WIFI_CODE is
signal s: unsigned (7 downto 0);--: inout STD_LOGIC;
begin

------------------------------------------
------ write operation on rising edge-----
------------------------------------------

div: process (RESET,CLOCK)
begin

if falling_edge (CLOCK) then

if (RESET = '1') then
CS <= '0';

--enable clock of 8MHz after 16ns
--CLOCK<=MASTER CLOCK;
--5ns delay
--writing and reading of data will occur at rising edge of clock

MOSI <="10101101"; --data out on MOSI line
s <= MOSI;
--MISO <='0';
else --if clock is not present
CS <= '1';
MOSI <="00000000";
s <= MOSI;
end if;

else
------------------------------------------
------ read operation on rising edge------
------------------------------------------

if (RESET = '1') then
CS <= '0';
s <= "10101101";
MISO <= s;
--MISO <='0';
else --if clock is not present
CS <= '1';
s <= "00000000";
MISO <= s;
end if;

end if;

end process;
DATA_IN <= std_logic_vector(s);
end Behavioral;


ERROR:
ERROR:HDLParsers:800 - "C:/FPGA projects/WIFI_CODE/WIFI_CODE.vhd" Line 85. Type of MISO is incompatible with type of s.
ERROR:HDLParsers:800 - "C:/FPGA projects/WIFI_CODE/WIFI_CODE.vhd" Line 90. Type of MISO is incompatible with type of s.
ERROR:HDLParsers:1402 - "C:/FPGA projects/WIFI_CODE/WIFI_CODE.vhd" Line 96. Object DATA_IN of mode IN can not be updated.
 
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Joined
Apr 11, 2014
Messages
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I don't think you have tried very hard to analyze these errors. The error messages are quite clear. Type of MISO is std_logic_vector; type of s is numeric_std--these types are incompatible. Either change the type of s or use type casting on one of the signals to make the assignment work. You cannot assign a value to an object of mode IN. If you need to change the value of an input, declare an internal signal (for example: i_DATA_IN), assign the input to that signal and then use the internal signal as needed. For example:

signal : i_DATA_IN : STD_LOGIC_VECTOR(7 downto 0);

i_DATA_IN <= DATA_IN;
i_DATA_IN <= std_logic_vector(s);
 

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