problem executing testbench. error in coding


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i'm using xilinx ise deign suite. i'm having problem with the testbench coding.

behavorial part

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity rom is
Port ( clk : in STD_LOGIC;
address : in integer range 0 to 7;
data_out : out STD_LOGIC_vector(2 downto 0));
end rom;

architecture Behavioral of rom is
signal reg_address : integer range 0 to 7;
type memory is array (0 to 7) of STD_LOGIC_vector(2 downto 0);
constant myrom : memory := (
1=>"001",
2=>"010",
3=>"011",
4=>"100",
5=>"101",
6=>"110",
7=>"111",
others =>"000");
begin
process(clk)
begin
if (clk'event and clk='1') then
reg_address<= address;
end if;
end process;
-----
data_out<= myrom(reg_address);
end Behavioral;

testbench coding(i have specified the syntax but i dont know how to correct it)

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY rom_tb IS
END rom_tb;

ARCHITECTURE behavior OF rom_tb IS --error here

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT rom_tb
PORT(
clk_tb : IN std_logic;
address_tb : IN std_logic_vector(0 to 7);
data_out_tb : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;


--Inputs
signal clk_tb : std_logic := '0';
signal address_tb : std_logic_vector(0 to 2) := (others => '0');

--Outputs
signal data_out_tb : std_logic_vector(2 downto 0);

-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: rom_tb PORT MAP (
clk_tb => clk_tb,
address_tb => address_tb,
data_out_tb => data_out_tb
);

-- Clock process definitions
clk_process : process
begin
clk_tb <= '0';
wait for clk_period/2;
clk_tb <= '1';
wait for clk_period/2;
end process;


-- Stimulus process
stim_proc: process
begin

-- hold reset state for 100 ns.
wait for 100 ns;

wait for clk_period*10;

-- insert stimulus here
clk_tb <= not clk_tb after 20ns ;
address_tb <='001' after 30ns, --error here
'010' after 60ns,
'011' after 90ns,
'100' after 120ns,
'101' after 150ns,
'110' after 180ns,
'111' after 210ns;
wait;
end process;
end architecture;
 
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Joined
Apr 11, 2014
Messages
3
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Your testbench has problems; try this:

Code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY rom_tb IS
END rom_tb;
ARCHITECTURE behavior OF rom_tb IS
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT rom
    PORT(
         clk : IN  std_logic;
         address : IN   integer range 0 to 7;
         data_out : OUT  std_logic_vector(2 downto 0)
        );
    END COMPONENT;
   

   --Inputs
   signal clk : std_logic := '0';
   signal address :  integer range 0 to 7;
   signal endsim : boolean := false;

     --Outputs
   signal data_out : std_logic_vector(2 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
BEGIN
    -- Instantiate the Unit Under Test (UUT)
   uut: rom PORT MAP (
          clk => clk,
          address => address,
          data_out => data_out
        );

   -- Clock process definitions
   clk_process :process
   begin
    while not endsim loop
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
        end loop;
        wait;
   end process;

   -- Stimulus process
   stim_proc: process
   begin       
      -- hold reset state for 100 ns.
      wait for 100 ns;   

      wait for clk_period*10;

      address <= 0;
      wait for 10 ns;
      address <= 1;
      wait for 10 ns;
      address <= 2;
      wait for 10 ns;
      address <= 3;
      wait for 10 ns;
      address <= 4;
      wait for 10 ns;
      address <= 5;
      wait for 10 ns;
      address <= 6;
      wait for 10 ns;
      address <= 7;
      wait for 10 ns;
      endsim <= true;
      wait;
   end process;

END;
 

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