Type mismatch in testbench

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Oct 4, 2011
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Hello everyone,

After fighting for hours with an vhdl code for a problem from a study-book I finaly got it to work (use quartus). But now I am fighting again with the code, but this time for the testbench for Modelsim. The error given seems easy to solve but I really don't know how to solve.

The code for my design is the next:

----- Package: ------------------------
library ieee;
use ieee.std_logic_1164.all;
----------------------------
package my_data_types is
constant m : integer := 8; -- width input-bus
type mux_inp is array (natural range <>) of std_logic_vector((m-1) downto 0);
end my_data_types;
----------------------------

----- Main: ---------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.my_data_types.all;
use ieee.std_logic_unsigned.all;
----------------------------
entity gen_mux is
generic (n : positive := 4); -- width selection-bus
port( x : in mux_inp (0 to 2**n-1); -- 2^n inputs
sel: in std_logic_vector (n-1 downto 0);
y: out std_logic_vector ((m-1) downto 0)); -- width output-bus
end gen_mux;
------ Architecture: --------------
architecture gen_mux of gen_mux is

begin
y <= x(conv_integer(sel));
end gen_mux;
-----------------------------------


Quartus made the next testbench (template writer) of it: (including my code)


-- Vhdl Test Bench template for design : gen_mux
--
-- Simulation tool : ModelSim-Altera (VHDL)
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE gen_mux_data_type IS
TYPE x_7_0_type IS ARRAY (7 DOWNTO 0) OF STD_LOGIC;
TYPE x_7_0_0_15_type IS ARRAY (0 TO 15) OF x_7_0_type;
SUBTYPE x_type IS x_7_0_0_15_type;
END gen_mux_data_type;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

library work;
use work.gen_mux_data_type.all;

ENTITY gen_mux_vhd_tst IS
END gen_mux_vhd_tst;
ARCHITECTURE gen_mux_arch OF gen_mux_vhd_tst IS
-- constants
-- signals
SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL x : x_type;
SIGNAL y : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT gen_mux IS
PORT (
sel : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
x : IN x_type;
y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
BEGIN
i1 : gen_mux
PORT MAP (
-- list connections between master ports and signals
sel => sel,
x => x,
y => y
);
init : PROCESS
-- variable declarations

BEGIN
-- code that executes only once

for i in 0 to sel'high loop
sel<= conv_std_logic_vector(i, sel'length);
wait for 50 ns;
end loop;

WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END gen_mux_arch;


After clicking the "EDA RTL Simulation" button, modelsim gives the next error:

# Reading C:/altera/11.0/modelsim_ase/tcl/vsim/pref.tcl
# do gen_mux_run_msim_rtl_vhdl.do
# if {[file exists rtl_work]} {
# vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying C:\altera\11.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied C:\altera\11.0\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
# Updated modelsim.ini.
#
# vcom -93 -work work {C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/gen_mux.vhd}
# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package my_data_types
# -- Loading package my_data_types
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity gen_mux
# -- Compiling architecture gen_mux of gen_mux
#
# vcom -93 -work work {C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/simulation/modelsim/gen_mux.vht}
# Model Technology ModelSim ALTERA vcom 6.6d Compiler 2010.11 Nov 2 2010
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling package gen_mux_data_type
# -- Loading package std_logic_arith
# -- Loading package gen_mux_data_type
# -- Compiling entity gen_mux_vhd_tst
# -- Compiling architecture gen_mux_arch of gen_mux_vhd_tst
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L maxii -L rtl_work -L work -voptargs="+acc" gen_mux_vhd_tst
# vsim -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L maxii -L rtl_work -L work -voptargs=\"+acc\" -t 1ps gen_mux_vhd_tst
# Loading std.standard
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading work.gen_mux_data_type
# Loading work.gen_mux_vhd_tst(gen_mux_arch)
# Loading work.my_data_types
# Loading ieee.std_logic_unsigned(body)
# Loading work.gen_mux(gen_mux)
# ** Failure: (vsim-3807) Types do not match between component and entity for port "x".
# Time: 0 ps Iteration: 0 Instance: /gen_mux_vhd_tst/i1 File: C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/gen_mux.vhd Line: 19
# Fatal error in file C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/gen_mux.vhd
# while elaborating region: /gen_mux_vhd_tst/i1
# Fatal error in file C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/simulation/modelsim/gen_mux.vht
# while elaborating region: /gen_mux_vhd_tst
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./gen_mux_run_msim_rtl_vhdl.do PAUSED at line 12

Does anybody know how I have to solve this?

Greets, Jan
 
Joined
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You should use exactly the same types in the component declaration as in the entity declaration:
Code:
library work;
use work.my_data_types.all;

ENTITY gen_mux_vhd_tst IS
END gen_mux_vhd_tst;
ARCHITECTURE gen_mux_arch OF gen_mux_vhd_tst IS
-- constants
constant n : positive := 4;
-- signals
SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL x : mux_inp (0 to 2**n-1);
SIGNAL y : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT gen_mux IS
generic (n : positive := 4); -- width selection-bus
port( x : in mux_inp (0 to 2**n-1); -- 2^n inputs
sel: in std_logic_vector (n-1 downto 0);
y: out std_logic_vector ((m-1) downto 0)); -- width output-bus
END COMPONENT;
BEGIN
  -- as before
END gen_mux_arch;
 
Joined
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Thank you for your reply. I have changed the code like you suggested.

-- Vhdl Test Bench template for design : gen_mux
--
-- Simulation tool : ModelSim-Altera (VHDL)
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

PACKAGE gen_mux_data_type IS
constant m : integer := 8; -- width input-bus
TYPE mux_inp IS ARRAY (natural range<>) OF STD_LOGIC_VECTOR (m-1 DOWNTO 0);
END gen_mux_data_type;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

library work;
use work.gen_mux_data_type.all;

ENTITY gen_mux_vhd_tst IS
END gen_mux_vhd_tst;
ARCHITECTURE gen_mux_arch OF gen_mux_vhd_tst IS
-- constants
constant n : positive := 4;
-- signals
SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL x : mux_inp (0 to 2**n-1);
SIGNAL y : STD_LOGIC_VECTOR(7 DOWNTO 0);
COMPONENT gen_mux IS
generic (n : positive := 4); -- width selection-bus
PORT (
sel: in std_logic_vector (n-1 downto 0);
x : in mux_inp (0 to 2**n-1); -- 2^n inputs
y: out std_logic_vector ((m-1) downto 0) -- width output-bus
);
END COMPONENT;
BEGIN
i1 : gen_mux
-- GENERIC MAP( n )
PORT MAP (
-- list connections between master ports and signals
sel => sel,
x => x,
y => y
);
init : PROCESS
-- variable declarations

BEGIN
-- code that executes only once

for i in 0 to 2**sel'high-1 loop
sel<= conv_std_logic_vector(i, sel'length);
wait for 50 ns;
end loop;

WAIT;
END PROCESS init;
always : PROCESS
-- optional sensitivity list
-- ( )
-- variable declarations
BEGIN
-- code executes for every event on sensitivity list
WAIT;
END PROCESS always;
END gen_mux_arch;

But Modelsim is still bugging me with the error:

** Failure: (vsim-3807) Types do not match between component and entity for port "x".
# Time: 0 ps Iteration: 0 Instance: /gen_mux_vhd_tst/i1 File: C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/gen_mux.vhd Line: 19
# Fatal error in file C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/gen_mux.vhd
# while elaborating region: /gen_mux_vhd_tst/i1
# Fatal error in file C:/Users/Stage/Desktop/rotzooimapje/problem5_1_V4/simulation/modelsim/gen_mux.vht
# while elaborating region: /gen_mux_vhd_tst
# Error loading design

How can there still be an error? How do the types still don't match? Is it some kind of conflict with library's or something?
 
Joined
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The only thing I can think of is that I don't see this:
Code:
use work.my_data_types.all;
in the code you just posted.
However if that's the cause, it would seem Modelsim should complain about not finding the type, not about 'not matching'.
 
Joined
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Thank you Joris,

It seems that you were right. This solved the problem. I guess because the test bench template writer also made the package that Modelsim didn't cry about not finding a type.

Now that the original package is included Modelsim started telling me that it doesn't know which constants to take. For example work.gen_mux_data_type.m or work.my_data_types.m. I solved this problem by throwing gen_mux_data_type out of the test bench.
Now Modelsim doesn't give errors anymore and just runs the test bench (which isn't complete).

Conclusion is that I learned never to use pre-made packages in test benches and just to include the original. Thank you for helping me learn this. :adore:

Greets, Jan
 

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