help with the testbench


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i have the following simple testbench and i cannot understand the error message..

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use std.textio.all;

entity tb_subtractor_n is
generic
(
N :integer := 8
);
end tb_subtractor_n;

architecture tb_arch of tb_subtractor_n is
component subtractor_n
generic
(
N :integer := 8
);
port
(
a,b: in std_logic_vector(N-1 downto 0);
bin: in std_logic;
d: out std_logic_vector(N-1 downto 0);
dout: out std_logic);
end component;

signal a : std_logic_vector(N-1 downto 0);
signal b : std_logic_vector(N-1 downto 0);
signal d : std_logic_vector(N-1 downto 0);
signal bin: std_logic;
signal dout: std_logic;
constant TIME_STEP : time := 1 ns;
begin
--here
UUT: subtractor_n
port map (
a=>a,
b=>b,
bin=>bin,
d=>d,
dout=>dout);

process

function a_minus_b(a,b:std_logic_vector(N-1 downto 0))--,bin:std_logic,d:std_logic_vector(N-1 downto 0),dout:std_logic)
return std_logic_vector is
begin
return a-b;
end a_minus_b;

begin

for a1 in std_logic'('0') to std_logic'('1') loop
for b1 in std_logic'('0') to std_logic'('1') loop
for c1 in std_logic'('0') to std_logic'('1') loop
for d1 in std_logic'('0') to std_logic'('1') loop
for e1 in std_logic'('0') to std_logic'('1') loop
for f1 in std_logic'('0') to std_logic'('1') loop
for g1 in std_logic'('0') to std_logic'('1') loop
for h1 in std_logic'('0') to std_logic'('1') loop
a<=a1&b1&c1&d1&e1&f1&g1&h1;
b<=a1&b1&c1&d1&e1&f1&g1&h1;
bin<='0';
wait for 5 ns;
assert(dout&d=a_minus_b(a,b));
report "Error";
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;
end loop;

end process;

end tb_arch;

error message:
** Error: (vsim-3732) C:/Modeltech_pe_edu_10.0a/examples/subtractor_n_tb.vhd(41): No default binding for component at 'UUT'.
# (Port 'dout' is not on the entity.)
# Region: /tb_subtractor_n/UUT
# Loading work.f_subtractor(truth_table)
# Error loading design
 
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Joined
Jan 29, 2009
Messages
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Are you sure the entity is called 'subtractor_n' instead of 'substractor_n' ?
 

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