IC 74374-getting incorrect simulation

Discussion in 'VHDL' started by xorro, Apr 26, 2019.

  1. xorro

    xorro

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    VHDL code is my implementation of ic74ls374. When i did the simulation i get 'U' at the start. I am currently learning vhdl so the code i wrote might be messy. I would appreciate any help.
    ic74374 datasheet--> http://ecee.colorado.edu/~mcclurel/dm74ls374.pdf

    Waveform
    wv.PNG
    Code (VHDL):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity ic74374 is
        port(
        oc:in std_logic;--OEx
        d1,d2,d3,d4,d5,d6,d7,d8:in std_logic;
        q1,q2,q3,q4,q5,q6,q7,q8:out std_logic;
        clk:in std_logic
        );
    end ic74374;

    architecture Behavioral of ic74374 is
       
    begin
        proc: process (oc,clk) is
        variable temp_q1,temp_q2,temp_q3,temp_q4,temp_q5,temp_q6,temp_q7,temp_q8:std_logic;
        variable impedance:std_logic:='Z';
        variable cur_temp_q1,cur_temp_q2,cur_temp_q3,cur_temp_q4,cur_temp_q5,cur_temp_q6,cur_temp_q7,cur_temp_q8:std_logic;
        variable prev_temp_q1,prev_temp_q2,prev_temp_q3,prev_temp_q4,prev_temp_q5,prev_temp_q6,prev_temp_q7,prev_temp_q8:std_logic;
        begin
            q1<=temp_q1;
            q2<=temp_q2;
            q3<=temp_q3;
            q4<=temp_q4;
            q5<=temp_q5;
            q6<=temp_q6;
            q7<=temp_q7;
            q8<=temp_q8;

            if(oc='0')then--oc ->output control
               
                if(rising_edge(clk))then
                             
                    if(prev_temp_q1='X')then
                        prev_temp_q1:=d1;
                        temp_q1:=prev_temp_q1;
                    else
                        cur_temp_q1:=d1;--temp_d1;
                        temp_q1:=cur_temp_q1;
                        prev_temp_q1:=cur_temp_q1;
                    end if;
                    ---------------------------------
                    if(prev_temp_q2='X')then
                        prev_temp_q2:=d2;
                        temp_q2:=prev_temp_q2;
                    else
                        cur_temp_q2:=d2;
                        temp_q2:=d2;--temp_d2;
                        prev_temp_q2:=cur_temp_q2;
                    end if;
                    ---------------------------------  
                    if(prev_temp_q3='X')then
                        prev_temp_q3:=d3;
                        temp_q3:=prev_temp_q3;
                    else
                        cur_temp_q3:=d3;
                        temp_q3:=d3;--temp_d3;
                        prev_temp_q3:=cur_temp_q3;
                    end if;
                    ---------------------------------  
                    if(prev_temp_q4='X')then
                        prev_temp_q4:=d4;
                        temp_q4:=prev_temp_q4;
                    else
                        cur_temp_q4:=d4;
                        temp_q4:=d4;--temp_d4;
                        prev_temp_q4:=cur_temp_q4;
                    end if;
                    ----------------------------------
                    if(prev_temp_q5='X')then
                        prev_temp_q5:=d5;
                        temp_q5:=prev_temp_q5;
                    else  
                        cur_temp_q5:=d5;
                        temp_q5:=d5;--temp_d5;
                        prev_temp_q5:=cur_temp_q5;
                    end if;
                    ----------------------------------
                    if(prev_temp_q6='X')then
                        prev_temp_q6:=d6;
                        temp_q6:=prev_temp_q6;
                    else
                        cur_temp_q6:=d6;
                        temp_q6:=d6;--temp_d6;
                        prev_temp_q6:=cur_temp_q6;
                    end if;
                    ----------------------------------
                    if(prev_temp_q7='X')then
                        prev_temp_q7:=d7;
                        temp_q7:=prev_temp_q7;
                    else  
                       cur_temp_q7:=d7;
                       temp_q7:=d7;--temp_d7;
                       prev_temp_q7:=cur_temp_q7;
                    end if;
                    ----------------------------------
                    if(prev_temp_q8='X')then
                        prev_temp_q8:=d8;
                        temp_q8:=prev_temp_q8;
                    else
                        cur_temp_q8:=d8;
                        temp_q8:=d8;--temp_d8;
                        prev_temp_q8:=cur_temp_q8;
                    end if;
                end if;
           
                if(clk'event and clk='0')then
                    temp_q1:=prev_temp_q1;
                    temp_q2:=prev_temp_q2;
                    temp_q3:=prev_temp_q3;
                    temp_q4:=prev_temp_q4;
                    temp_q5:=prev_temp_q5;
                    temp_q6:=prev_temp_q6;
                    temp_q7:=prev_temp_q7;
                    temp_q8:=prev_temp_q8;
                end if;
            elsif(oc='1')then
                temp_q1:=impedance;
                temp_q2:=impedance;
                temp_q3:=impedance;
                temp_q4:=impedance;
                temp_q5:=impedance;
                temp_q6:=impedance;
                temp_q7:=impedance;
                temp_q8:=impedance;
            end if;
       
        end process;

    end Behavioral;
               
    Testbench
    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    entity ic74374_tb is
    --  Port ( );
    end ic74374_tb;

    architecture Behavioral of ic74374_tb is
        component ic74374 is
        port(
        oc:in std_logic;--OEx
        d1,d2,d3,d4,d5,d6,d7,d8:in std_logic;
        q1,q2,q3,q4,q5,q6,q7,q8:out std_logic;
        clk:in std_logic
        );
        end component;
       
        signal oc: std_logic;--OEx
        signal d1,d2,d3,d4,d5,d6,d7,d8: std_logic;
        signal q1,q2,q3,q4,q5,q6,q7,q8: std_logic;
        signal clk: std_logic:='1';
       
    begin
        uut: ic74374 port map(
        oc=>oc,
        clk=>clk,
        d1=>d1,
        d2=>d2,
        d3=>d3,
        d4=>d4,
        d5=>d5,
        d6=>d6,
        d7=>d7,
        d8=>d8,
        q1=>q1,
        q2=>q2,
        q3=>q3,
        q4=>q4,
        q5=>q5,
        q6=>q6,
        q7=>q7,
        q8=>q8
        );
       
        clk<= not clk after 50ns;
       
        sim: process begin
            d1<='1';
            d2<='0';
            d3<='1';
            d4<='0';
            d5<='1';
            d6<='0';
            d7<='1';
            d8<='0';
            oc<='0';
            wait for 100ns;
            d1<='0';
            oc<='0';
            wait for 600ns;
            oc<='0';
            wait for 100ns;
            oc<='0';
            wait;
        end process;

    end Behavioral;
     
     
    xorro, Apr 26, 2019
    #1
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