Can anyone please help me in this code

[ragerrani]

Intro: The sign-magnitude format is an alternative way to represent a signed number. It is used for floating-point representation. In this format, the MSB is the sign bit (0 for positive and 1 for negative) and the remaining bits represent the magnitude. For example, in 5-bit sign-magnitude format, “01001” represents +9 and “11001” represents -9.
Write VHDL code can perform addition and subtraction for numbers in sign-magnitude format. The inputs of the circuit are

a, b: the two 5-bit input operands in sign-magnitude format.

add: a 1-bit signal indicating the type of operation, in which 0 is for addition (i.e., a+b) and 1 is for subtraction (i.e., a-b).

The output of the circuit is

r: the 5-bit result in sign-magnitude format.

Hint:
entity sm_arith is port (

a, b: in std_logic_vector(4 downto 0); add: in std_logic;

r: out std_logic_vector(4 downto 0)

); end sm_arith;

preform this calculations:
(+5) + (+3), (+5) + (3), (5) + (+3), (-5) + (-3),

(+5) - (+3), (+5) - (-3), (-5) - (+3), (-5) - (-3)

 

[TheAliceMay]

Intro: The sign-magnitude format is an alternative way to represent a signed number. It is used for floating-point representation. In this format, the MSB is the sign bit (0 for positive and 1 for negative) and the remaining bits represent the magnitude. For example, in 5-bit sign-magnitude format, “01001” represents +9 and “11001” represents -9.
Write VHDL code can perform addition and subtraction for numbers in sign-magnitude format. The inputs of the circuit are

a, b: the two 5-bit input operands in sign-magnitude format.

add: a 1-bit signal indicating the type of operation, in which 0 is for addition (i.e., a+b) and 1 is for subtraction (i.e., a-b).

The output of the circuit is

r: the 5-bit result in sign-magnitude format.

Hint:
entity sm_arith is port (

a, b: in std_logic_vector(4 downto 0); add: in std_logic;

r: out std_logic_vector(4 downto 0)

); end sm_arith;

preform this calculations:
(+5) + (+3), (+5) + (3), (5) + (+3), (-5) + (-3),

(+5) - (+3), (+5) - (-3), (-5) - (+3), (-5) - (-3)

There are "libraries" that help you with 'SIGNED' and 'UNSIGNED' addition and subtraction. They are:

library ieee;
use ieee.std_logic_1164.all; -- which you are using
use ieee.numeric_std.all;

Keep in mind. The "+" and "-" operations are identical for positive and negative numbers; a caveat, negative numbers should be represented in two's-complement format. You are using signed-maginitude. In which case I would use the 'UNSIGNED' type, detect the most significant bit for magnitude and perform the appropriate operation.

Here's a great post: https://www.nandland.com/vhdl/examples/example-signed-unsigned.html