Write VHDL code can perform addition and subtraction for numbers in sign-magnitude format. The inputs of the circuit are

a, b: the two 5-bit input operands in sign-magnitude format.

add: a 1-bit signal indicating the type of operation, in which 0 is for addition (i.e., a+b) and 1 is for subtraction (i.e., a-b).

The output of the circuit is

r: the 5-bit result in sign-magnitude format.

Hint:

entity sm_arith is port (

a, b: in std_logic_vector(4 downto 0); add: in std_logic;

r: out std_logic_vector(4 downto 0)

); end sm_arith;

preform this calculations:

(+5) + (+3), (+5) + (3), (5) + (+3), (-5) + (-3),

(+5) - (+3), (+5) - (-3), (-5) - (+3), (-5) - (-3)