VHDL Subtraction two’s complement


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The entity shall implement the following arithmetic functionality:
• Substraction I1 - I2
• Input operand 1 (I1): 12 bit, two’s complement
• Input operand 2 (I2): 8 bit, two’s complement
• Output (O): 12 bit, two’s complement
• Overflow (V) and Carry flag (C) set accordingly
• Valid flag (VALID): indicates if the computed solution is valid or not

So what I have done?

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity arithmetic is

port( I1 :in std_logic_vector(12-1 downto 0); -- Operand 1

I2 :in std_logic_vector(8-1 downto 0); -- Operand 2

O : Out std_logic_vector(12-1 downto 0); -- Output

C : Out std_logic; -- Carry Flag

V : Out std_logic; -- Overflow Flag

VALID : Out std_logic -- Flag to indicate if the solution is valid or not

);

end arithmetic;

architecture behavior of arithmetic is

begin

process(I1,I2)

begin

if ((unsigned(I1)-unsigned(I2)) > unsigned(I1)) and
((unsigned(I1)-unsigned(I2)) > unsigned(I2)) then

C <= '1';

else

C <= '0';

end if;

if I1(11)='1' and signed(std_logic_vector(unsigned(I1)-unsigned(I2)))>0
then

V <= '1';

else

V <= '0';

end if;

if unsigned(I1) < unsigned(I2) then

VALID <= '0';

else

VALID <= '1';

end if;

O <= std_logic_vector(unsigned(I1)-unsigned(I2));

end process;

end behavior;


There is no syntax mistakes or something like that. Only mistake is
that:


Error for:

comp2,SUB

I1= 100000011110

I2= 01000001

Expected:

O= 011111011101

C= '0', V= '1', VALID= '0'

Received:

O= 011111011101

C= '0', V= '1' and VALID= '1'


If someone could help I would be really thankful.
 
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