wimax interleaver

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library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cf_interleaver_10_32_5 is

port (

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(0 downto 0);

i4 : in unsigned(0 downto 0);

i5 : in unsigned(1 downto 0);

o1 : out unsigned(0 downto 0));

end entity cf_interleaver_10_32_5;

architecture rtl of cf_interleaver_10_32_5 is

signal n1 : unsigned(1 downto 0);

signal n2 : unsigned(1 downto 0);

signal n3 : unsigned(1 downto 0);

signal n4 : unsigned(0 downto 0);

signal n5 : unsigned(0 downto 0);

signal n6 : unsigned(0 downto 0);

signal n7 : unsigned(0 downto 0);

signal n8 : unsigned(0 downto 0);

signal n9 : unsigned(0 downto 0);

begin

n1 <= "00";

n2 <= "10";

n3 <= "01";

n4 <= "1" when i5 = n1 else "0";

n5 <= "1" when i5 = n2 else "0";

n6 <= "1" when i5 = n3 else "0";

n7 <= i2 when n6 = "1" else i1;

n8 <= i3 when n5 = "1" else n7;

n9 <= i4 when n4 = "1" else n8;

o1 <= n9;

end architecture rtl;


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cf_interleaver_10_32_4 is

port (

i1 : in unsigned(1 downto 0);

o1 : out unsigned(0 downto 0));

end entity cf_interleaver_10_32_4;

architecture rtl of cf_interleaver_10_32_4 is

signal n1 : unsigned(0 downto 0);

signal n2 : unsigned(0 downto 0);

signal n3 : unsigned(1 downto 0);

signal n4 : unsigned(1 downto 0);

signal n5 : unsigned(0 downto 0);

signal n6 : unsigned(0 downto 0);

signal n7 : unsigned(0 downto 0);

signal n8 : unsigned(0 downto 0);

signal n9 : unsigned(0 downto 0);

begin

n1 <= "0";

n2 <= "0";

n3 <= "00";

n4 <= "10";

n5 <= "1" when i1 = n3 else "0";

n6 <= "1" when i1 = n4 else "0";

n7 <= n1 when n6 = "1" else n9;

n8 <= n2 when n5 = "1" else n7;

n9 <= "1";

o1 <= n8;

end architecture rtl;


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cf_interleaver_10_32_3 is

port (

clock_c : in std_logic;

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(0 downto 0);

o1 : out unsigned(0 downto 0));

end entity cf_interleaver_10_32_3;

architecture rtl of cf_interleaver_10_32_3 is

signal n1 : unsigned(0 downto 0);

signal n2 : unsigned(0 downto 0);

signal n3 : unsigned(0 downto 0);

signal n4 : unsigned(0 downto 0);

signal n5 : unsigned(1 downto 0);

signal n6 : unsigned(0 downto 0) := "0";

signal s7_1 : unsigned(0 downto 0);

signal s8_1 : unsigned(0 downto 0);

component cf_interleaver_10_32_5 is

port (

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(0 downto 0);

i4 : in unsigned(0 downto 0);

i5 : in unsigned(1 downto 0);

o1 : out unsigned(0 downto 0));

end component cf_interleaver_10_32_5;

component cf_interleaver_10_32_4 is

port (

i1 : in unsigned(1 downto 0);

o1 : out unsigned(0 downto 0));

end component cf_interleaver_10_32_4;

begin

n1 <= "0";

n2 <= "1";

n3 <= "1";

n4 <= "0";

n5 <= i3 & n6;

process (clock_c) begin

if rising_edge(clock_c) then

if i2 = "1" then

n6 <= "0";

elsif i1 = "1" then

n6 <= s7_1;

end if;

end if;

end process;

s7 : cf_interleaver_10_32_5 port map (n1, n2, n3, n4, n5, s7_1);

s8 : cf_interleaver_10_32_4 port map (n5, s8_1);

o1 <= s8_1;

end architecture rtl;


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cf_interleaver_10_32_2 is

port (

clock_c : in std_logic;

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(0 downto 0);

i4 : in unsigned(0 downto 0);

i5 : in unsigned(9 downto 0);

i6 : in unsigned(31 downto 0);

o1 : out unsigned(0 downto 0);

o2 : out unsigned(0 downto 0);

o3 : out unsigned(31 downto 0));

end entity cf_interleaver_10_32_2;

architecture rtl of cf_interleaver_10_32_2 is

signal n1 : unsigned(9 downto 0);

signal n2 : unsigned(9 downto 0);

signal n3 : unsigned(9 downto 0) := "0000000000";

signal n4 : unsigned(0 downto 0);

signal n5 : unsigned(0 downto 0) := "0";

signal n6 : unsigned(9 downto 0);

signal n7 : unsigned(0 downto 0);

signal n8 : unsigned(0 downto 0);

signal n9 : unsigned(31 downto 0);

signal n9a : unsigned(9 downto 0) := "0000000000";

type n9mt is array (1023 downto 0) of unsigned(31 downto 0);

signal n9m : n9mt;

signal n10 : unsigned(0 downto 0);

signal n11 : unsigned(31 downto 0);

signal n11a : unsigned(9 downto 0) := "0000000000";

type n11mt is array (1023 downto 0) of unsigned(31 downto 0);

signal n11m : n11mt;

signal n12 : unsigned(0 downto 0) := "0";

signal n13 : unsigned(31 downto 0);

signal s14_1 : unsigned(0 downto 0);

component cf_interleaver_10_32_3 is

port (

clock_c : in std_logic;

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(0 downto 0);

o1 : out unsigned(0 downto 0));

end component cf_interleaver_10_32_3;

begin

n1 <= "0000000001";

n2 <= n3 + n1;

process (clock_c) begin

if rising_edge(clock_c) then

if i3 = "1" then

n3 <= "0000000000";

elsif i1 = "1" then

n3 <= n2;

end if;

end if;

end process;

n4 <= not s14_1;

process (clock_c) begin

if rising_edge(clock_c) then

if i2 = "1" then

n5 <= "0";

elsif i1 = "1" then

n5 <= i3;

end if;

end if;

end process;

n6 <= "0000000000";

n7 <= "1" when n3 = n6 else "0";

n8 <= i4 and n4;

process (clock_c) begin

if rising_edge(clock_c) then

if i1 = "1" then

if n8 = "1" then

n9m(to_integer(i5)) <= i6;

end if;

n9a <= n3;

end if;

end if;

end process;

n9 <= n9m(to_integer(n9a));

n10 <= i4 and s14_1;

process (clock_c) begin

if rising_edge(clock_c) then

if i1 = "1" then

if n10 = "1" then

n11m(to_integer(i5)) <= i6;

end if;

n11a <= n3;

end if;

end if;

end process;

n11 <= n11m(to_integer(n11a));

process (clock_c) begin

if rising_edge(clock_c) then

if i2 = "1" then

n12 <= "0";

elsif i1 = "1" then

n12 <= n4;

end if;

end if;

end process;

n13 <= n11 when n12 = "1" else n9;

s14 : cf_interleaver_10_32_3 port map (clock_c, i1, i2, i3, s14_1);

o3 <= n13;

o2 <= n7;

o1 <= n5;

end architecture rtl;


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cf_interleaver_10_32_1 is

port (

clock_c : in std_logic;

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(9 downto 0);

i4 : in unsigned(31 downto 0);

o1 : out unsigned(0 downto 0);

o2 : out unsigned(0 downto 0);

o3 : out unsigned(31 downto 0));

end entity cf_interleaver_10_32_1;

architecture rtl of cf_interleaver_10_32_1 is

signal n1 : unsigned(0 downto 0);

signal n2 : unsigned(0 downto 0);

signal s3_1 : unsigned(0 downto 0);

signal s3_2 : unsigned(0 downto 0);

signal s3_3 : unsigned(31 downto 0);

component cf_interleaver_10_32_2 is

port (

clock_c : in std_logic;

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(0 downto 0);

i4 : in unsigned(0 downto 0);

i5 : in unsigned(9 downto 0);

i6 : in unsigned(31 downto 0);

o1 : out unsigned(0 downto 0);

o2 : out unsigned(0 downto 0);

o3 : out unsigned(31 downto 0));

end component cf_interleaver_10_32_2;

begin

n1 <= "1";

n2 <= "0";

s3 : cf_interleaver_10_32_2 port map (clock_c, n1, n2, i1, i2, i3, i4, s3_1, s3_2, s3_3);

o3 <= s3_3;

o2 <= s3_2;

o1 <= s3_1;

end architecture rtl;


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity cf_interleaver_10_32 is

port(

signal clock_c : in std_logic;

signal swap_i : in unsigned(0 downto 0);

signal write_i : in unsigned(0 downto 0);

signal addr_i : in unsigned(9 downto 0);

signal data_i : in unsigned(31 downto 0);

signal sync_primary_o : out unsigned(0 downto 0);

signal sync_secondary_o : out unsigned(0 downto 0);

signal data_o : out unsigned(31 downto 0));

end entity cf_interleaver_10_32;

architecture rtl of cf_interleaver_10_32 is

component cf_interleaver_10_32_1 is

port (

clock_c : in std_logic;

i1 : in unsigned(0 downto 0);

i2 : in unsigned(0 downto 0);

i3 : in unsigned(9 downto 0);

i4 : in unsigned(31 downto 0);

o1 : out unsigned(0 downto 0);

o2 : out unsigned(0 downto 0);

o3 : out unsigned(31 downto 0));

end component cf_interleaver_10_32_1;

signal n1 : unsigned(0 downto 0);

signal n2 : unsigned(0 downto 0);

signal n3 : unsigned(31 downto 0);

begin

s1 : cf_interleaver_10_32_1 port map (clock_c, swap_i, write_i, addr_i, data_i, n1, n2, n3);

sync_primary_o <= n1;

sync_secondary_o <= n2;

data_o <= n3;

end architecture rtl;
here is the coding for wimax interleaver no error is found but while simulation the output of cf_interleaver_32_10_2 is always undefined.any one please help me to generate the output
 

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