E

#### Emmanuel

I've written a package but getting compilation errors in modelsim

in which i cant figure out if anyone can it will be of helpful. the

errors are

1)enc_pkg.vhd(61): near "and": expecting ';'

2)enc_pkg.vhd(106): near "1": expecting ')'

3)enc_pkg.vhd(123): near "0": expecting ')'

4)enc_pkg.vhd(146): (vcom-1272) Length of expected is 20; length of

actual is 10.---particularly here in this error I expect 10 bit

deprecation but it is showing error

the code part:

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

package enc_pkg is

constant n : integer := 1;

constant k : integer := 2;

constant m : integer := 3;

constant L_total : integer := 10;

constant L_info : integer := 10;

type t_g is array (1 downto 1, 3 downto 1)of std_logic;

signal g:t_g;

type array3_10 is array (3 downto 1, 10 downto 0) of std_logic;

type array2_10 is array (2 downto 1, 10 downto 0) of std_logic;

procedure rsc_encoder(

x : in std_logic_vector(1 to 10);

terminated : in std_logic;

y : out array2_10);

procedure encode_bit(input : in std_logic;

state_in : in std_logic_vector(1 to 2);

output : out std_logic_vector(1 to 2);

state_out : out std_logic_vector(1 to 2));

procedure encoderm

(infor_bit : in std_logic_vector(1 to 8);

en_output : out std_logic_vector(1 to 20));

end enc_pkg;

package body enc_pkg is

procedure rsc_encoder(

x : in std_logic_vector(1 to 10);

terminated : in std_logic;

y : out array2_10)is

variable state : std_logic_vector(1 to 2);

variable d_k : std_logic;

variable a_k : std_logic;

variable output_bit : std_logic_vector(1 to 2);

variable state_out : std_logic_vector(1 to 2);

begin

for i in 1 to m loop

state(i) := '0';

end loop;

for i in 1 to L_total loop

if(terminated = '0' or (terminated = '1' and i <= L_info))

then

d_k := x(i);

elsif(terminated = '1' and i > L_info)then

d_k := (g(1, 2) and state(1)) xor (g(1, 3) and

state(2));

end if;

a_k := (g(1, 1) and d_k) xor (g(1, 2) and

state(1)) xor (g(1, 3)) and state(2));

encode_bit(a_k, state, output_bit, state_out);

state := state_out;

output_bit(1) := d_k;

y(1, i) := output_bit(1);

y(2, i) := output_bit(2);

end loop;

end rsc_encoder;

procedure encode_bit(input : in std_logic;

state_in : in std_logic_vector(1 to 2);

output : out std_logic_vector(1 to 2);

state_out : out std_logic_vector(1 to 2))is

variable temp : std_logic_vector(1 to 2);

begin

for i in 1 to n loop

temp(i) := g(i, 1) and input;

for j in 2 to k loop

temp(i) := temp(i) xor (g(i, j) and state_in(j-1));

end loop;

end loop;

output := temp;

state_out := input & state_in(m-1);

end encode_bit;

procedure encoderm

(infor_bit : in std_logic_vector(1 to 8);

en_output : out std_logic_vector(1 to 20))is

--type array2_10 is array (2 downto 1, 10 downto 0) of integer;

--type array3_10 is array (3 downto 1, 10 downto 0) of integer;

variable interleaved : std_logic_vector(1 to 10);

variable input : std_logic_vector(1 to 10);

variable puncture : std_logic;

variable output : array3_10;

variable y : array2_10;

variable en_temp : std_logic_vector(1 to 10);

begin

input := "0000000000";

for i in 1 to 8 loop

input(i) := infor_bit(i);

end loop;

rsc_encoder(input, terminated 1, y);

for i in 1 to 10 loop

output(1, i) := y(1, i);

output(2, i) := y(2, i);

end loop;

interleaved(1) := output(1, 1);

interleaved(2) := output(1, 4);

interleaved(3) := output(1, 7);

interleaved(4) := output(1, 10);

interleaved(5) := output(1, 2);

interleaved(6) := output(1, 5);

interleaved(7) := output(1, 8);

interleaved(8) := output(1, 3);

interleaved(9) := output(1, 6);

interleaved(10) := output(1, 9);

rsc_encoder(interleaved, terminated 0, y);

for i in 1 to 10 loop

output(3, i) := y(2, i);

end loop;

if puncture = '1'then

for i in 1 to 10 loop

for j in 1 to 3 loop

en_output(3*(i-1)+j) := output(j, i);

end loop;

end loop;

elsif puncture = '0' then

for i in 1 to L_total loop

en_temp(n*(i-1)+1) := output(1, i);

if((i rem 2) = 1)then

en_temp(n*i) := output(2, i);

else

en_temp(n*i) := output(3, i);

end if;

end loop;

end if;

en_output := en_temp;

end encoderm;

end enc_pkg;