Alu


Joined
Nov 12, 2009
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hi guys!! i'm new to VHDL and i'm trying to design an ALU for a project. I want to use components and "case".. here is my code... but i don't have any idea how to enter the components in the case... can anyone please help me??


entity ALU is

port (
opcode:in std_logic_vector (2 downto 0);
A,B :in std_logic_vector (3 downto 0);
Output:eek:ut std_logic_vector(3 downto 0);
zero:eek:ut std_logic

);
end ALU;

architecture Behavioral of ALU is


component nand_gate
port (
a: in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
c:eek:ut std_logic_vector (3 downto 0)
);
end component;


component and_gate
port (
a: in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
c:eek:ut std_logic_vector (3 downto 0)
);
end component;


component nor_gate
port (
a: in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
c:eek:ut std_logic_vector (3 downto 0)
);
end component;


component or_gate
port (
a: in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
c:eek:ut std_logic_vector (3 downto 0)
);
end component;


component xor_gate
port (
a: in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
c:eek:ut std_logic_vector (3 downto 0)
);
end component;


component xnor_gate
port (
a: in std_logic_vector (3 downto 0);
b:in std_logic_vector (3 downto 0);
c:eek:ut std_logic_vector (3 downto 0)
);
end component;



begin

n1:nand_gate
port map (
a=>A,
b=>B,
c=>Output
);

n2:and_gate
port map (
a=>A,
b=>B,
c=>Output
);

n3:nor_gate
port map (
a=>A,
b=>B,
c=>Output
);

n4:eek:r_gate
port map (
a=>A,
b=>B,
c=>Output
);

n5:xor_gate
port map (
a=>A,
b=>B,
c=>Output
);

n6:xnor_gate
port map (
a=>A,
b=>B,
c=>Output
);


process (opcode,A,B)
begin
case(opcode) is
when "011" =>

when "100" =>

when "101" =>

when "110" =>

when "111" =>

when "010" =>

when "001" => If A=B then zero<= '1';
end if;
when others => output <= "0000";
end case;

end process;


end Behavioral;
 
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Joined
Jan 29, 2009
Messages
152
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0
Might try something like this:
Code:
signal  result : std_logic_vector(6 downto 1);

begin

n1:nand_gate
port map (
a=>A,
b=>B,
c=>result(1)
);

n2:and_gate
port map (
a=>A,
b=>B,
c=>result(2)
);

n3:nor_gate
port map (
a=>A,
b=>B,
c=>result(3)
);

n4:xor_gate
port map (
a=>A,
b=>B,
c=>result(4)
);

n5:nor_gate
port map (
a=>A,
b=>B,
c=>result(5)
);

n6:xnor_gate
port map (
a=>A,
b=>B,
c=>result(6)
);


process (opcode,A,B)
begin
case(opcode) is
when "011" => Output <= result(1);

when "100" => Output <= result(2);

when "101" => Output <= result(3);

when "110" => Output <= result(4);

when "111" => Output <= result(5);

when "010" => Output <= result(6);

when "001" => If A=B then zero<= '1';
end if;
when others => output <= "0000";
end case;

end process;
 
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