entity ALU is

port (

opcode:in std_logic_vector (2 downto 0);

A,B :in std_logic_vector (3 downto 0);

Outputut std_logic_vector(3 downto 0);

zerout std_logic

);

end ALU;

architecture Behavioral of ALU is

component nand_gate

port (

a: in std_logic_vector (3 downto 0);

b:in std_logic_vector (3 downto 0);

cut std_logic_vector (3 downto 0)

);

end component;

component and_gate

port (

a: in std_logic_vector (3 downto 0);

b:in std_logic_vector (3 downto 0);

cut std_logic_vector (3 downto 0)

);

end component;

component nor_gate

port (

a: in std_logic_vector (3 downto 0);

b:in std_logic_vector (3 downto 0);

cut std_logic_vector (3 downto 0)

);

end component;

component or_gate

port (

a: in std_logic_vector (3 downto 0);

b:in std_logic_vector (3 downto 0);

cut std_logic_vector (3 downto 0)

);

end component;

component xor_gate

port (

a: in std_logic_vector (3 downto 0);

b:in std_logic_vector (3 downto 0);

cut std_logic_vector (3 downto 0)

);

end component;

component xnor_gate

port (

a: in std_logic_vector (3 downto 0);

b:in std_logic_vector (3 downto 0);

cut std_logic_vector (3 downto 0)

);

end component;

begin

n1:nand_gate

port map (

a=>A,

b=>B,

c=>Output

);

n2:and_gate

port map (

a=>A,

b=>B,

c=>Output

);

n3:nor_gate

port map (

a=>A,

b=>B,

c=>Output

);

n4r_gate

port map (

a=>A,

b=>B,

c=>Output

);

n5:xor_gate

port map (

a=>A,

b=>B,

c=>Output

);

n6:xnor_gate

port map (

a=>A,

b=>B,

c=>Output

);

process (opcode,A,B)

begin

case(opcode) is

when "011" =>

when "100" =>

when "101" =>

when "110" =>

when "111" =>

when "010" =>

when "001" => If A=B then zero<= '1';

end if;

when others => output <= "0000";

end case;

end process;

end Behavioral;