trimming of wanted (useful) signals in XILINX board what is the problem of my code

[corin.otesteanu]

I'm implementing a finite state machine to count some events.

The pre-synthesis simulations works fine, but the post synthesis doesn't. Im sure it's because of the trimming:

FF/Latch <pr_state_FSM_FFd3> has a constant value of 0 in block <fsm_moving_object>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <pr_state_FSM_FFd1> has a constant value of 0 in block <fsm_moving_object>. This FF/Latch will be trimmed during the optimization process.

Any help would be appreciated.

Here is my code:

entity fsm_moving_object is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC;
B : in STD_LOGIC;
res : in STD_LOGIC;
output: out STD_LOGIC_vector(3 downto 0));
end fsm_moving_object;

architecture Behavioral of fsm_moving_object is

type states is (state0, stateA, state_inc, stateB, state_dec);
signal pr_state, next_state: states;
signal index: integer range 0 to 9:=0;
signal A_prev: std_logic :='0';
signal B_prev: std_logic:='0';

begin

process (res, clk,index)
begin
if (res='1') then
pr_state <= state0;
elsif (clk'event and clk = '1') then
pr_state <= next_state;
output<=Conv_Std_Logic_Vector(index,4);
end if;
end process;

process (pr_state,A,B,res)
variable inc: integer range 0 to 1;
variable dec: integer range 0 to 1;
begin
inc:=0;
dec:=0;
case pr_state is
when state0 =>
if (A='0' and A_prev='1') then
next_state<= stateA;
elsif (B='0' and B_prev='1') then
next_state<=stateB;
else next_state<=state0;
end if;

when stateA =>
if (B='0' and B_prev='1') then next_state<= state_inc;
elsif (A='0' and A_prev='1') then next_state<= state0;
else next_state<=stateA;
end if;

when state_inc=>
inc:=1;
next_state<=state0;

when stateB =>
if (B='0' and B_prev='1' ) then next_state<= state0;
elsif (A='0' and A_prev='1' ) then next_state<= state_dec;
else next_state<=stateB;
end if;

when state_dec=>
dec:=1;
next_state<=state0;
end case;

if (res='1') then
A_prev<='0';
B_prev<='0';
index<=0;
else
A_prev<=A;
B_prev<=B;
index<=index+inc-dec;
end if;
end process;
end Behavioral;

 

[corin.otesteanu]

Problem solved.
If interested, you can read what exactly was the problem and how i solved it here:
http://forums.xilinx.com/t5/Spartan...what-is-the/m-p/146812/highlight/false#M10967