simulation help

J

jeffreywhite2011

Hi all,

I'm using Xilinx iSim to simulate a system in which I'd like to run a 32-point fft followed by an 128 point fft. I'm using counters to simulate the ffts. I've tried a state-machine implementation, but when I run the sim, the input to the state machine goes to an 'X' instead of a '1' when the counterin the 32-point fft process hits it's final value of ten. Also, the state never goes from state0 to state 1.

the way I thought it would work is:

1. the system starts in state0 and the input to the state machine is 0.
2. the 32-point process counts to 10 and then sets the input to '1'.
3. the state changes to state1.
4. the 128 point process counts to 30 and then sets the input to '0'.

My code can be seen below.

thank you for your help.

Jeff White

----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity stateMachineWfft_32pt is
end stateMachineWfft_32pt;


architecture Behavioral of stateMachineWfft_32pt is

constant CLOCK_PERIOD : time := 100 ns;

signal aclk : std_logic := '0'; -- the master clock
signal input : std_logic := '0'; -- the thing that makes the state machine do stuff

type state_type is (state0, state1);
signal current_state : state_type;
signal next_state : state_type;


begin

-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------

clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;

fft_128pt : process(aclk, input)
variable count1 : integer := 0;
begin
if(current_state = state1 and aclk'event and aclk = '1' ) then
count1 := count1 + 1;
if(count1 = 30) then
input <='0';
end if;
end if;
end process fft_128pt;

------------------------------------------------------------------------
-- implement a fft_32pt to 10 and then return a value signifying completion
------------------------------------------------------------------------

fft_32pt : process(aclk, input)

variable count : integer := 0;

begin
if(current_state = state0 and aclk'event and aclk = '1') then
count := count + 1;
if(count = 10) then
input <= '1';
end if;
end if;
end process fft_32pt;


state_machine : process( current_state, input )
begin
--
case current_state is
when state0 =>
if(input = '0') then
next_state <= state0;
elsif (input = '1') then
next_state <= state1;
end if;
when state1 =>
if(input = '1') then
next_state <= state1;
elsif (input ='0') then
next_state <= state0;
end if;
end case;
--
end process state_machine;


----------------------------------------------------------------------------------
-- implement the transfer of next state to current state
----------------------------------------------------------------------------------

state_update : process (aclk)
begin

if( rising_edge(aclk)) then
current_state <= next_state;
end if;
end process state_update;

end Behavioral;
 
J

jeffreywhite2011

Hi all,



I'm using Xilinx iSim to simulate a system in which I'd like to run a 32-point fft followed by an 128 point fft. I'm using counters to simulate the ffts. I've tried a state-machine implementation, but when I run the sim, the input to the state machine goes to an 'X' instead of a '1' when the counter in the 32-point fft process hits it's final value of ten. Also, the state never goes from state0 to state 1.



the way I thought it would work is:



1. the system starts in state0 and the input to the state machine is 0.

2. the 32-point process counts to 10 and then sets the input to '1'.

3. the state changes to state1.

4. the 128 point process counts to 30 and then sets the input to '0'.



My code can be seen below.



thank you for your help.



Jeff White



----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;



-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;



-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;



entity stateMachineWfft_32pt is

end stateMachineWfft_32pt;





architecture Behavioral of stateMachineWfft_32pt is



constant CLOCK_PERIOD : time := 100 ns;



signal aclk : std_logic := '0'; -- the master clock

signal input : std_logic := '0'; -- the thing that makes the state machine do stuff



type state_type is (state0, state1);

signal current_state : state_type;

signal next_state : state_type;





begin



-----------------------------------------------------------------------

-- Generate clock

-----------------------------------------------------------------------



clock_gen : process

begin

aclk <= '0';

wait for CLOCK_PERIOD;

loop

aclk <= '0';

wait for CLOCK_PERIOD/2;

aclk <= '1';

wait for CLOCK_PERIOD/2;

end loop;

end process clock_gen;



fft_128pt : process(aclk, input)

variable count1 : integer := 0;

begin

if(current_state = state1 and aclk'event and aclk = '1' ) then

count1 := count1 + 1;

if(count1 = 30) then

input <='0';

end if;

end if;

end process fft_128pt;



------------------------------------------------------------------------

-- implement a fft_32pt to 10 and then return a value signifying completion

------------------------------------------------------------------------



fft_32pt : process(aclk, input)



variable count : integer := 0;



begin

if(current_state = state0 and aclk'event and aclk = '1') then

count := count + 1;

if(count = 10) then

input <= '1';

end if;

end if;

end process fft_32pt;





state_machine : process( current_state, input )

begin

--

case current_state is

when state0 =>

if(input = '0') then

next_state <= state0;

elsif (input = '1') then

next_state <= state1;

end if;

when state1 =>

if(input = '1') then

next_state <= state1;

elsif (input ='0') then

next_state <= state0;

end if;

end case;

--

end process state_machine;





----------------------------------------------------------------------------------

-- implement the transfer of next state to current state

----------------------------------------------------------------------------------



state_update : process (aclk)

begin



if( rising_edge(aclk)) then

current_state <= next_state;

end if;

end process state_update;



end Behavioral;
I changed the process signatures to

fft_128pt : process(aclk, current_state) and
fft_32pt : process(aclk, currentat_state)

with no change in the behavior of the simulation.
 
J

jeffreywhite2011

Hi all,



I'm using Xilinx iSim to simulate a system in which I'd like to run a 32-point fft followed by an 128 point fft. I'm using counters to simulate the ffts. I've tried a state-machine implementation, but when I run the sim, the input to the state machine goes to an 'X' instead of a '1' when the counter in the 32-point fft process hits it's final value of ten. Also, the state never goes from state0 to state 1.



the way I thought it would work is:



1. the system starts in state0 and the input to the state machine is 0.

2. the 32-point process counts to 10 and then sets the input to '1'.

3. the state changes to state1.

4. the 128 point process counts to 30 and then sets the input to '0'.



My code can be seen below.



thank you for your help.



Jeff White



----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;



-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;



-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;



entity stateMachineWfft_32pt is

end stateMachineWfft_32pt;





architecture Behavioral of stateMachineWfft_32pt is



constant CLOCK_PERIOD : time := 100 ns;



signal aclk : std_logic := '0'; -- the master clock

signal input : std_logic := '0'; -- the thing that makes the state machine do stuff



type state_type is (state0, state1);

signal current_state : state_type;

signal next_state : state_type;





begin



-----------------------------------------------------------------------

-- Generate clock

-----------------------------------------------------------------------



clock_gen : process

begin

aclk <= '0';

wait for CLOCK_PERIOD;

loop

aclk <= '0';

wait for CLOCK_PERIOD/2;

aclk <= '1';

wait for CLOCK_PERIOD/2;

end loop;

end process clock_gen;



fft_128pt : process(aclk, input)

variable count1 : integer := 0;

begin

if(current_state = state1 and aclk'event and aclk = '1' ) then

count1 := count1 + 1;

if(count1 = 30) then

input <='0';

end if;

end if;

end process fft_128pt;



------------------------------------------------------------------------

-- implement a fft_32pt to 10 and then return a value signifying completion

------------------------------------------------------------------------



fft_32pt : process(aclk, input)



variable count : integer := 0;



begin

if(current_state = state0 and aclk'event and aclk = '1') then

count := count + 1;

if(count = 10) then

input <= '1';

end if;

end if;

end process fft_32pt;





state_machine : process( current_state, input )

begin

--

case current_state is

when state0 =>

if(input = '0') then

next_state <= state0;

elsif (input = '1') then

next_state <= state1;

end if;

when state1 =>

if(input = '1') then

next_state <= state1;

elsif (input ='0') then

next_state <= state0;

end if;

end case;

--

end process state_machine;





----------------------------------------------------------------------------------

-- implement the transfer of next state to current state

----------------------------------------------------------------------------------



state_update : process (aclk)

begin



if( rising_edge(aclk)) then

current_state <= next_state;

end if;

end process state_update;



end Behavioral;
I figured it out. Thanks for reading.

jw
 

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