Issue with simulation time - Modelsim PE Student 10.4

Discussion in 'VHDL' started by Rashnak, Jun 21, 2016.

  1. Rashnak

    Rashnak

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    Dear all,

    I'm very new to VHDL and got an issue with the simulation time in Modelsim 10.4.

    I wrote some files for a RTL-model such as multiplexer, demultiplexer and register.
    To test my code I tried to implement a testbench for each file. The simulation for the multiplexer and demultiplexer work quite well but the testbench for the registers seems to simulate for ever. Whenever I try to simulate nothing happens and the simulation doesn't finish at any point. I tried to look at the wave forms but they change neither.

    Following I will send you the corresponding code for my 4x1-MUX (which works quite well) and code for my 12bit register with synchronous reset (which doesn't simulate correctly).

    I really can't find the problem by myself so I appreciate if someone could help me. :)



    -- multiplexer for 4 inputs with 12 bit data width to 1 output with 12 bit data width

    entity MULTIPLEXER_4TO1_12BIT is
    port (
    SELECT_IN: in bit_vector (1 downto 0);
    D_IN_0: in bit_vector (11 downto 0);
    D_IN_1: in bit_vector (11 downto 0);
    D_IN_2: in bit_vector (11 downto 0);
    D_IN_3: in bit_vector (11 downto 0);
    D_OUT: out bit_vector (11 downto 0)
    );
    end MULTIPLEXER_4TO1_12BIT;

    architecture RTL of MULTIPLEXER_4TO1_12BIT is
    begin
    D_OUT <= D_IN_0 when SELECT_IN = "00" else
    D_IN_1 when SELECT_IN = "01" else
    D_IN_2 when SELECT_IN = "10" else
    D_IN_3;
    end RTL;


    -- testbench for multiplexer for 4 inputs with 12 bit data width to 1 output with 12 bit data width

    entity TESTBENCH_MULTIPLEXER_4TO1_12BIT is
    end TESTBENCH_MULTIPLEXER_4TO1_12BIT;

    architecture BEHAVIOUR of TESTBENCH_MULTIPLEXER_4TO1_12BIT is
    signal SELECT_IN: bit_vector (1 downto 0) := "00";
    signal D_IN_0, D_IN_1, D_IN_2, D_IN_3, D_OUT : bit_vector (11 downto 0) := B"0000_0000_0000";
    begin
    UUT: entity work.MULTIPLEXER_4TO1_12BIT port map (SELECT_IN, D_IN_0, D_IN_1, D_IN_2, D_IN_3, D_OUT);
    tb: process
    begin
    D_IN_0 <= B"0000_0000_0000";
    D_IN_1 <= B"0001_0001_0001";
    D_IN_2 <= B"0110_0110_0110";
    D_IN_3 <= B"1111_1111_1111";
    SELECT_IN <= "00";
    wait for 2 ns;
    SELECT_IN <= "01";
    wait for 2 ns;
    SELECT_IN <= "10";
    wait for 2 ns;
    SELECT_IN <= "11";
    wait for 2 ns;

    assert false report "end of simulation" severity failure;
    end process tb;
    end BEHAVIOUR;



    -- register with 12 bit data width and synchronous reset

    entity REG_SYNC_12BIT is
    port (
    D_IN: in bit_vector (11 downto 0);
    CLK: in bit;
    EN: in bit;
    RST: in bit;
    D_OUT: out bit_vector (11 downto 0)
    );
    end REG_SYNC_12BIT;

    architecture RTL of REG_SYNC_12BIT is
    begin
    process
    begin
    if (rising_edge (CLK)) then
    if (RST = '0') then
    D_OUT <= B"0000_0000_0000";
    else
    if (EN = '1') then
    D_OUT <= D_IN;
    end if;
    end if;
    end if;
    end process;
    end RTL;


    -- testbench for register with 12 bit data width and synchronous reset

    entity TESTBENCH_REG_SYNC_12BIT is
    end TESTBENCH_REG_SYNC_12BIT;

    architecture BEHAVIOUR of TESTBENCH_REG_SYNC_12BIT is
    signal D_IN, D_OUT: bit_vector (11 downto 0) := B"0000_0000_0000";
    signal CLK, EN: bit := '0';
    signal RST: bit := '1';

    begin
    UUT: entity work.REG_SYNC_12BIT port map (D_IN, CLK, EN, RST, D_OUT);
    stim_proc: process
    begin
    EN <= '1';
    D_IN <= B"1111_1111_1111";
    wait for 4 ns;
    CLK <= '1';
    wait for 2 ns;
    D_IN <= B"0000_1111_1111";
    wait for 2 ns;
    CLK <= '1';
    wait for 10 ns;
    assert false report "end of simulation" severity failure;
    end process;
    end BEHAVIOUR;
     
    Rashnak, Jun 21, 2016
    #1
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  2. Rashnak

    Rashnak

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    This post can be closed.

    The answer to my simulation problem is that I forgot to add CLK and RST to the sensitivity list of the process in the RTL-architecture of the register.
     
    Rashnak, Jun 22, 2016
    #2
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