Modelsim - Simulation Fatal Error

[vino_TUM]

Hi,

Here is the code of my state machine
"
--------------------------------------------------------
type monfsm_reg_type is record
state : STATE_TYPE;
start : std_logic;
address : std_logic_vector(31 downto 0);
wdata : std_logic_vector(31 downto 0);
inst_cnt : std_logic_vector(5 downto 0); -- instance counter (eg no. of leons)
pword_cnt : std_logic_vector(5 downto 0); -- packet word counter (eg in current spec 5 32bit word constitutes a packet)
end record;

------------------------------------------

fsm_combo_logic: process (c,fsm_start_I, dmao, lpact, bpact) is
variable v : monfsm_reg_type;
begin
v := c;
---- FSM Mux ----
case c.state is
when ST_IDLE =>
if (fsm_start_I = '1') then
v.state := ST_AHB_WAIT;
end if;
when ST_AHB_WAIT =>
if (dmao.ready = '1') then
v.state := ST_LPACKETS_Tx;
end if;
when ST_LPACKETS_Tx =>
if (c.inst_cnt = NLCPUM1 and c.pword_cnt = MCFG_PWORDSM1) then
v.state := ST_BPACKETS_Tx;
end if;
when ST_BPACKETS_Tx =>
if (c.pword_cnt = MCFG_PWORDSM1) then
v.state := ST_IDLE;
end if;
when others => null;
end case;
------------
if ((v.state = ST_AHB_WAIT) or (v.state = ST_LPACKETS_Tx) or (v.state = ST_BPACKETS_Tx)) then
v.start := '1';
end if;
if (dmao.ready = '1') then
v.inst_cnt := c.inst_cnt+1;
v.pword_cnt := c.pword_cnt+1;
if dmao.haddr = (9 downto 0 => '0') then
v.address := (c.address(31 downto 10) + 1) & dmao.haddr;
else
v.address := c.address(31 downto 10) & dmao.haddr;
end if;
if (v.state = ST_LPACKETS_Tx) then
case v.pword_cnt is
when "000000" => v.wdata := lpact(conv_integer(v.inst_cnt)).data0;
when "000001" => v.wdata := lpact(conv_integer(v.inst_cnt)).data1; ------ERROR LINE
when "000010" => v.wdata := lpact(conv_integer(v.inst_cnt)).data2;
when "000011" => v.wdata := lpact(conv_integer(v.inst_cnt)).data3;
when "000100" => v.wdata := lpact(conv_integer(v.inst_cnt)).data4;
when others => null;
end case;
end if;
if (v.state = ST_BPACKETS_Tx) then
case v.pword_cnt is
when "000000" => v.wdata := bpact.data0;
when "000001" => v.wdata := bpact.data1;
when "000010" => v.wdata := bpact.data2;
when "000011" => v.wdata := bpact.data3;
when "000100" => v.wdata := bpact.data4;
when others => null;
end case;
end if;
if (c.inst_cnt = NLCPUM1 or c.state = ST_IDLE) then
v.inst_cnt := (others => '0'); end if;
if (c.pword_cnt = MCFG_PWORDSM1 or c.state = ST_IDLE) then
v.pword_cnt := (others => '0'); end if;
if (c.state = ST_IDLE) then v.address := TARGET_ADDRESS; end if;
end if;
-- Reset Condition
if (rst_I = '0') then
v.state := ST_IDLE;
v.start := '0';
v.address := TARGET_ADDRESS;
v.wdata := (others => '0');
v.inst_cnt := (others => '0');
v.pword_cnt := (others => '0');
end if;
-- DMA inputs
dmai.wdata <= c.wdata;
dmai.burst <= '1';
dmai.irq <= '0';
dmai.size <= "10";
dmai.write <= '0';
dmai.busy <= '0';
dmai.start <= c.start;
dmai.address <= c.address;
-- Temporary variable to next state 'signal'
n <= v;
end process fsm_combo_logic;

--------------------------------------------------------------------------

-- FSM seq
proc_clk : process(clk_I)
begin
if rising_edge(clk_I) then
c <= n; -- next state 'signal' to current state 'signal'
end if;
end process proc_clk;

"

Code compiles properly; but during simulation, after one ms when it reaches the line (mentioned as "ERROR LINE" above), Modelsim throws the error

** Fatal: (vsim-3421) value 1 is out of range 0 to 0;

I am using variables for first time in my state machine design.
If I change the v.inst_cnt to c.inst_cnt, it works fine.... but with variable in RHS this error comes,....
when "000001" => v.wdata := lpact(conv_integer(v.inst_cnt)).data1;
So, I am clueless about the cause of this error.
Any suggestions ?

Thanks in advance.

Regards
vino_TUM

 

[vino_TUM]

Error Fixed

Hi,....

My mistake,.... variable v.inst_cnt is getting incremented before the above mentioned case statement, which is checked for upper limit only it has been used by the case statement.
Thats the cause for the ERROR.