addition not work in vhdl

[marcin00022]

Hello
I want to draw squere 50 x 50 pixel on the screen (640 x 480) begining in mouse position

but it change size .. somtimes it is (20 x 50) or (50 x 30) or (30 x 30) and i don't have slightest idea what is wrong ...

code:



librarposy IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entitposy ACursor is
port (
clk: in STD_LOGIC;

posy: in STD_LOGIC_VECTOR (9 downto 0);
posx: in STD_LOGIC_VECTOR (9 downto 0) ;
cursor_posy_in: in STD_LOGIC_VECTOR (7 downto 0);
cursor_posx_in: in STD_LOGIC_VECTOR (7 downto 0) ;

ro : out STD_LOGIC_VECTOR (2 downto 0);
go : out STD_LOGIC_VECTOR (2 downto 0);
bo : out STD_LOGIC_VECTOR (2 downto 0);
ri : in STD_LOGIC_VECTOR (2 downto 0);
gi : in STD_LOGIC_VECTOR (2 downto 0);
bi : in STD_LOGIC_VECTOR (2 downto 0)

);
end ACursor;

architecture behaviour of ACursor is

signal cursor_posy: unsigned (9 downto 0);
signal cursor_posx: unsigned (9 downto 0) ;
begin
cursor_posy <= unsigned(cursor_posy_in(6 downto 0) & "000");
cursor_posx <= unsigned(cursor_posx_in(6 downto 0) & "000");

process(posx,posy)
begin

if(rising_edge(clk)) then
if (unsigned(posx) < 4) or (unsigned(posx) > 636) or (unsigned(posy) < 5) or (unsigned(posy) > 477) then
ro <= "000";
go <= "000";
bo <= "000";

elsif (( unsigned(posx) = cursor_posx) OR (unsigned(posx) = ((cursor_posx) + x"32")) or (unsigned(posy) = cursor_posy) OR (unsigned(posy) = ((cursor_posy)+ x"32" ))) and
(( unsigned(posx) >= cursor_posx) and (unsigned(posx) <= ((cursor_posx) + x"33")) and (unsigned(posy) >= cursor_posy) and (unsigned(posy) <= ((cursor_posy)+ x"33" ))) then

ro <= "111";
go <= "000";
bo <= "000";

else
ro <= ri;
go <= gi;
bo <= bi;
end if;
end if;

end process;
end behaviour;

It feels like it's not adding properly

 

[Bart Fox]

Hello
I want to draw squere 50 x 50 pixel on the screen (640 x 480) begining in mouse position

but it change size .. somtimes it is (20 x 50) or (50 x 30) or (30 x 30) and i don't have slightest idea what is wrong ...

code: [...]
It feels like it's not adding properly

Change feelings with knowledge!
Just write a testbench.

regards
Bart

 

[Vipin Lal]

Instead of process(posx,posy) ,

Use process(clk).

Not sure whether it will change the mentioned error, but you need to change the sensitivity list anyway.

 

[marcin00022]

the sensitivity list can't be the case becoiuse is only for symulator anyway.

and I vreated the test bench like sugest Bart and everything is fine ...

so my feelings based on knowledge is that some optimalization or place and route behave different than i asume ...

And that is not the first time when orginal project not work but symulation does

That why i am asking if I broke some rule in this code ...

 

[Bart Fox]

Hello Marcin!

and I vreated the test bench like sugest Bart and everything is fine ...

Can you publish your testbench?
So maybe others (and I) are able to check it.

regards,
Bart

 

[Thomas Stanka]

Am Samstag, 24. August 2013 21:52:40 UTC+2 schrieb (e-mail address removed):

the sensitivity list can't be the case becoiuse is only for symulator anyway.

and I vreated the test bench like sugest Bart and everything is fine ...

If you build testbench and compare simualtion result to real behavior and see differences, you have sensitivity list as one possible source of differences. I would eliminate all obvious problems first before starting to spend time with debug of the high sophisticated bugs.

so my feelings based on knowledge is that some optimalization or place and route behave different than i asume ...
And that is not the first time when orginal project not work but symulation does
That why i am asking if I broke some rule in this code ...

The code itself seems fine to me when it comes to differences between simulation and real world if you would correct the sensitivity list.

But this is only half of physical design.

A major source of differences between simulation and real device are wrong treated asynchronous interfaces. Next source would be wrong application of timing analysis.

Maybe there is an input in your design asynchronous to clock that is not proper handled(eg 2stage FF)?
Are you sure you did static timing analysis (STA) correct?
Did you perform backannotated simulation with this design and is that equivalent to behavioral simulation?

best regards

Thomas

 

[pini]

Hello
I want to draw squere 50 x 50 pixel on the screen (640 x 480) begining in mouse position

but it change size .. somtimes it is (20 x 50) or (50 x 30) or (30 x 30) and i don't have slightest idea what is wrong ...

code:



librarposy IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.ALL;

entitposy ACursor is
port (
clk: in STD_LOGIC;

posy: in STD_LOGIC_VECTOR (9 downto 0);
posx: in STD_LOGIC_VECTOR (9 downto 0) ;
cursor_posy_in: in STD_LOGIC_VECTOR (7 downto 0);
cursor_posx_in: in STD_LOGIC_VECTOR (7 downto 0) ;

ro : out STD_LOGIC_VECTOR (2 downto 0);
go : out STD_LOGIC_VECTOR (2 downto 0);
bo : out STD_LOGIC_VECTOR (2 downto 0);
ri : in STD_LOGIC_VECTOR (2 downto 0);
gi : in STD_LOGIC_VECTOR (2 downto 0);
bi : in STD_LOGIC_VECTOR (2 downto 0)

);
end ACursor;

architecture behaviour of ACursor is

signal cursor_posy: unsigned (9 downto 0);
signal cursor_posx: unsigned (9 downto 0) ;
begin
cursor_posy <= unsigned(cursor_posy_in(6 downto 0) & "000");
cursor_posx <= unsigned(cursor_posx_in(6 downto 0) & "000");

process(posx,posy)
begin

if(rising_edge(clk)) then
if (unsigned(posx) < 4) or (unsigned(posx) > 636) or (unsigned(posy) < 5) or (unsigned(posy) > 477) then
ro <= "000";
go <= "000";
bo <= "000";

elsif (( unsigned(posx) = cursor_posx) OR (unsigned(posx) = ((cursor_posx) + x"32")) or (unsigned(posy) = cursor_posy) OR (unsigned(posy) = ((cursor_posy)+ x"32" ))) and
(( unsigned(posx) >= cursor_posx) and (unsigned(posx) <= ((cursor_posx) + x"33")) and (unsigned(posy) >= cursor_posy) and (unsigned(posy) <= ((cursor_posy)+ x"33" ))) then

ro <= "111";
go <= "000";
bo <= "000";

else
ro <= ri;
go <= gi;
bo <= bi;
end if;
end if;

end process;
end behaviour;

It feels like it's not adding properly

here is an addition example, works fine and tested with GHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.STD_LOGIC_UNSIGNED.conv_integer;
use ieee.STD_LOGIC_UNSIGNED."+";
...
--average caclulation
signal average_q : std_logic_vector( 7 downto 0);
signal average_i : std_logic_vector( 7 downto 0);
signal average_p : std_logic_vector( 8 downto 0);
...
p_clk : process (rx_clk,reset)
begin
...
elsif rising_edge(rx_clk) then
...
average_q >= average_i;
...
--average
average_i >=
average_p(8 downto 1) when fsm_ps(c_loc_ave0) = '1' else average_q;
average_p >= std_logic_vector(
unsigned('0' & mem_do(39 downto 32)) + unsigned('0' & i_ttl)
);

this example is discussed in
h===://bknpk.no-ip.biz/my_web/SDIO/ip_ttl_filter_vhdl_averaege.html
As part of IP TTL filter implemented in VHDL, using a bench with linked lists ...