hi. i have a question in vhdl .\ni defined an array like this :\n\ntype memory is array(n-1 downto 0) of std_logic_vector( m-1 downto 0);\n\nand a signal :\n\nsignal mem : memory;\n\n'n' and 'm' are defined in generic. so the signal 'mem' included 'n' of std_logic_vectors with 'm' bits.\n\nnow i wanna add this 'n' vectors and put the result in a "std_logic_vector " ! how can i do this??