sum of a array's element

Discussion in 'VHDL' started by alireza95, Jun 28, 2018.

  1. alireza95

    alireza95

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    hi. i have a question in vhdl .
    i defined an array like this :

    type memory is array(n-1 downto 0) of std_logic_vector( m-1 downto 0);

    and a signal :

    signal mem : memory;

    'n' and 'm' are defined in generic. so the signal 'mem' included 'n' of std_logic_vectors with 'm' bits.

    now i wanna add this 'n' vectors and put the result in a "std_logic_vector " ! how can i do this??
     
    alireza95, Jun 28, 2018
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