Lattice EFB I2C core works in simulation, but not on hardware


L

littlegamer

Hello,

Perhaps someone with Lattice experience can answer this for me. I am building a design on a MachXO2 using the EFB for I2C slave communication. I builtmy own state machine for writing and reading to the wishbone bus. In simulation, it works perfectly. I can read and write to the I2C lines, see what the wishbone bus is doing, data is processed correctly. In simulation. WhenI synthesize the design and feed it to an actual MachXO2, it doesn't work at all. The I2C core is alive, it responds to addresses by sending ACKs, also when writing data, but when trying to read the exact same address, it feeds me rubbish (like 0x0B or 0x0F), repeatedly writing will cause the device to crash by pulling the SDA or SCL lines hard low.

I'm using the internal oscillator at 8MHz portmapped to the Wishbone bus. I've changed the statemachine to do the same thing specified in the reference designs (as in, discarding the read buffer twice, disabling and re-enabling the interrupt source for TRRDY, waiting for BUSY low etc). Apart from the extra wishbone transactions, simulation results and hardware results remain the same. I have no clue where to look for. Can anyone give me pointers?

Regards,
littlegamer
 
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A

alb

Hi littlegamer,

On 23/10/2013 19:00, littlegamer wrote:
[]
Perhaps someone with Lattice experience can answer this for me. I am
building a design on a MachXO2 using the EFB for I2C slave
communication. I built my own state machine for writing and reading
to the wishbone bus. In simulation, it works perfectly. I can read
and write to the I2C lines, see what the wishbone bus is doing, data
is processed correctly. In simulation. When I synthesize the design
and feed it to an actual MachXO2, it doesn't work at all.

have you run a post-synth simulation? Have you performed static timing
analysis? If not I strongly invite you to do so before going on the bench.
The I2C
core is alive, it responds to addresses by sending ACKs, also when
writing data, but when trying to read the exact same address, it
feeds me rubbish (like 0x0B or 0x0F), repeatedly writing will cause
the device to crash by pulling the SDA or SCL lines hard low.

Be aware that often simulation vs. reality mismatches are due to
'incomplete simulation environment'. Check that all the input to your
logic is properly modeled in your simulation, including timing and most
of all power-up/rst sequence.

HTH,

Al

p.s.: How do you define a 'device crash'? I've seen a car crash
yesterday and I bet that I do not have to explain you what a car crash
is. My suggestion: try to describe your problem according to your
observations, not to your - understandable - frustration for having a
not working hardware.
 
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Hi littlegamer and alb...

My situation is little different.. I am trying EFB Secondary I2c as a master , with Wishbone Master inside my logic.
I have success in Reading and Writing EFB registers and have properly written all registers like TXDR, Command Register, Control Register of Secondary i2c . But in simulation i dont see any kind of activity in SCL and SDA lines from EFB primitive block...
Both lines are always in High Impedence (Blue in Modelsim, Green if Aldec Simulator Used).
In Test Bench i do
1. An initial Reset
2. Enable I2c core by writing 0x80 to 0x4a register(Control)
3. Write Clock Prescale Registers 0x4c and 0x4d with proper value
4. Read back and verified these registers
5. Wrote Data 0xF1to TXDR register
6. Issued 0x94 to Command Register for a (Start + Write)

But i dont see any activity in SCL , SDA liness....

Am i missing something here.. Any help would be very helpful... Thanks....


Device : MACHXO2-7000
Tool : Lattice Diamond 3.1.0.96 (64 bit)
 
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Hello,

Perhaps someone with Lattice experience can answer this for me. I am building a design on a MachXO2 using the EFB for I2C slave communication. I builtmy own state machine for writing and reading to the wishbone bus. In simulation, it works perfectly. I can read and write to the I2C lines, see what the wishbone bus is doing, data is processed correctly. In simulation. WhenI synthesize the design and feed it to an actual MachXO2, it doesn't work at all. The I2C core is alive, it responds to addresses by sending ACKs, also when writing data, but when trying to read the exact same address, it feeds me rubbish (like 0x0B or 0x0F), repeatedly writing will cause the device to crash by pulling the SDA or SCL lines hard low.

I'm using the internal oscillator at 8MHz portmapped to the Wishbone bus. I've changed the statemachine to do the same thing specified in the reference designs (as in, discarding the read buffer twice, disabling and re-enabling the interrupt source for TRRDY, waiting for BUSY low etc). Apart from the extra wishbone transactions, simulation results and hardware results remain the same. I have no clue where to look for. Can anyone give me pointers?

Regards,
littlegamer

I didn't try on wishbone by I2C but direct access through wishbone port to read TRACE ID. Trace ID data is coped to RAM in other code to have easy access later. It works in machxo3lf HW. Below you can find code with wishbone access.

However I am curious how were you able to simulate wishbone. I am using Modelsim and vhdl. I have warning I cannot pass.
Component instance "EFB_M : EFB" is not bound. EFB is simply not simulated in library I have created based on c:\lscc\diamond\3.11_x64\cae_library\simulation\vhdl\machxo3l\src\ MACHX03L vhdl files)
Similar issue I have for SEDFA and SEDFB components from MACHXO3LCOMP.vhd. The issue is architecture is not provided in MACHXO3L_MISC.vhd.
How did you make EFB work in simulation? Where to look for code with architecture ?


entity wishbone_my is
port (
reset: in std_logic; -- global reset
enable: in std_logic; -- valid cycle
strobe: in std_logic; -- strobe
wren: in std_logic; -- write enable
addr: in byte; -- address
datain: in byte; -- data input
dataout: out byte; -- data output
ack: out std_logic; -- transfer acknowledge
clock: in std_logic -- main clock
);
end entity;


architecture my of wishbone_my is


begin


EFB_M: EFB generic map (
DEV_DENSITY => "6900L",
EFB_WB_CLK_FREQ => "40.0",
GSR => "ENABLED"
) port map (
WBCLKI => clock,
WBRSTI => reset,
WBCYCI => enable,
WBSTBI => strobe,
WBWEI => wren,
WBADRI7 => addr(7),
WBADRI6 => addr(6),
WBADRI5 => addr(5),
WBADRI4 => addr(4),
WBADRI3 => addr(3),
WBADRI2 => addr(2),
WBADRI1 => addr(1),
WBADRI0 => addr(0),
WBDATI7 => datain(7),
WBDATI6 => datain(6),
WBDATI5 => datain(5),
WBDATI4 => datain(4),
WBDATI3 => datain(3),
WBDATI2 => datain(2),
WBDATI1 => datain(1),
WBDATI0 => datain(0),
PLL0DATI7 => '0',
PLL0DATI6 => '0',
PLL0DATI5 => '0',
PLL0DATI4 => '0',
PLL0DATI3 => '0',
PLL0DATI2 => '0',
PLL0DATI1 => '0',
PLL0DATI0 => '0',
PLL0ACKI => '0',
PLL1DATI7 => '0',
PLL1DATI6 => '0',
PLL1DATI5 => '0',
PLL1DATI4 => '0',
PLL1DATI3 => '0',
PLL1DATI2 => '0',
PLL1DATI1 => '0',
PLL1DATI0 => '0',
PLL1ACKI => '0',
I2C1SCLI => '0',
I2C1SDAI => '0',
I2C2SCLI => '0',
I2C2SDAI => '0',
SPISCKI => '0',
SPIMISOI => '0',
SPIMOSII => '0',
SPISCSN => '0',
TCCLKI => '0',
TCRSTN => '0',
TCIC => '0',
UFMSN => '1',
WBDATO7 => dataout(7),
WBDATO6 => dataout(6),
WBDATO5 => dataout(5),
WBDATO4 => dataout(4),
WBDATO3 => dataout(3),
WBDATO2 => dataout(2),
WBDATO1 => dataout(1),
WBDATO0 => dataout(0),
WBACKO => ack,
PLLCLKO => open,
PLLRSTO => open,
PLL0STBO => open,
PLL1STBO => open,
PLLWEO => open,
PLLADRO4 => open,
PLLADRO3 => open,
PLLADRO2 => open,
PLLADRO1 => open,
PLLADRO0 => open,
PLLDATO7 => open,
PLLDATO6 => open,
PLLDATO5 => open,
PLLDATO4 => open,
PLLDATO3 => open,
PLLDATO2 => open,
PLLDATO1 => open,
PLLDATO0 => open,
I2C1SCLO => open,
I2C1SCLOEN => open,
I2C1SDAO => open,
I2C1SDAOEN => open,
I2C2SCLO => open,
I2C2SCLOEN => open,
I2C2SDAO => open,
I2C2SDAOEN => open,
I2C1IRQO => open,
I2C2IRQO => open,
SPISCKO => open,
SPISCKEN => open,
SPIMISOO => open,
SPIMISOEN => open,
SPIMOSIO => open,
SPIMOSIEN => open,
SPIMCSN7 => open,
SPIMCSN6 => open,
SPIMCSN5 => open,
SPIMCSN4 => open,
SPIMCSN3 => open,
SPIMCSN2 => open,
SPIMCSN1 => open,
SPIMCSN0 => open,
SPICSNEN => open,
SPIIRQO => open,
TCINT => open,
TCOC => open,
WBCUFMIRQ => open,
CFGWAKE => open,
CFGSTDBY => open
);


end architecture;
 

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