conv_std_logic_vector

Discussion in 'VHDL' started by trescot, Dec 12, 2006.

  1. trescot

    trescot Guest

    Hello

    I am new to VHDL.

    I have something like

    CONV_STD_LOGIC_VECTOR(16#6800#,16);

    what does it mean?


    Thanks
    Trescot
     
    trescot, Dec 12, 2006
    #1
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  2. 16#6800# is an integer to the base 16 (hexadecimal) and would be written
    in C as 0x6800.

    conv_std_logic_vector is a conversion function from a
    non-standard-package and is NOT recommended to use! It converts an
    integer to a std_logic_vector.
    The function has two arguments: the integer value to be converted and an
    integer number of bits. You can assign the result to a signal / variable
    of type e.g. std_logic_vector(15 downto 0).

    Ralf
     
    Ralf Hildebrandt, Dec 12, 2006
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  3. trescot

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    it helped

    thanks,
    I just joined the forum because of your help.
    I hope to be of help to others too
     
    , Aug 21, 2009
    #3
  4. trescot

    CarterTheBest

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    Ralf so, could you write another way to do this conversion?
    I use this function to assign a decimal value to std_logic_vector, because I don't like to recount my value every time to hexadecimal or binary. I have a variable length vector (the length was defined in generic section) and want to change it's value in VHDL test bench to do a simulation.
     
    CarterTheBest, Apr 21, 2010
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  5. trescot

    joris

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    using only standard functions, this does the same conversion:

    std_logic_vector(to_unsigned(16#6800#,16))
     
    joris, Apr 23, 2010
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  6. trescot

    bala6007

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    hello ,


    LVL1 <= conv_std_logic_vector(A1+D1,6);
    how can i convert this into verilog ?
    can any one help me?
     
    bala6007, Dec 27, 2018
    #6
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