Length of Range

[Brad Smallridge]

I have this code:

subtype field1 is natural range 15 downto 0;
....
begin

memory_data_out_updaterocess(clk)
begin
....
if(condition)then
mem_do(field1)<=conv_std_logic_vector(128,16);
else
mem_do(field1)<=mem_di(8)(field1);
end if;
....

Mem_di(8)() is a clocked delayed version
of the memory input from a previous read cycle.

What I would like to do is automatically
calculate the "length" of the field1 range
and put it in the conv_std_logic_vector
parameters so that I can change my fields
definitions without changing the
conv_std_logic_vector code.

Brad Smallridge
AiVision

 

[Mike Treseler]

What I would like to do is automatically
calculate the "length" of the field1 range

I would use field1'length

-- Mike Treselre

 

[KJ]

I have this code:

subtype field1 is natural range 15 downto 0;
...
begin

memory_data_out_updaterocess(clk)
begin
...
if(condition)then
  mem_do(field1)<=conv_std_logic_vector(128,16);
else
  mem_do(field1)<=mem_di(8)(field1);
end if;
...

Mem_di(8)() is a clocked delayed version
of the memory input from a previous read cycle.

What I would like to do is automatically
calculate the "length" of the field1 range
and put it in the conv_std_logic_vector
parameters so that I can change my fields
definitions without changing the
conv_std_logic_vector code.

Brad Smallridge
AiVision

I'm assuming (perhaps incorrectly) that 'field1' is some sub-field of
some larger structure, then what I do is define a record with that
collection of fields like this

type t_MY_COLLECTION is record
Field1: std_ulogic_vector(15 downto 0);
Field2: std_ulogic_vector(31 downto 16);
end record t_MY_COLLECTION;

Then I create 'to_std_logic_vector' and 'from_std_logic_vector'
functions that convert the record to and from std_logic_vectors. The
record definition and the to/from functions get put into a package.

To get the length of the field you use...
t_MY_COLLECTION.Field1'length
or
Some_Sig.Field1'length (Some_Sig is of type t_MY_COLLECTION).

Now when any field within the record changes size, the ONLY edit you
will make is to the t_MY_COLLECTION record and then recompile. No
other edits required anywhere, everything gets adjusted and you don't
end up with having to do more than one edit and forgetting to do it
somewhere else

If interested, peruse the following links for previous posts where
I've gone into more detail
http://groups.google.com/group/comp...?hl=en&q=to_std_logic_vector+"Kevin+Jennings"

http://groups.google.com/group/comp...?hl=en&q=to_std_logic_vector+"Kevin+Jennings"

Kevin Jennings

 

[Brad Smallridge]

How about

constant field_length: integer := field1'high + 1 - field1'low;

Thanks, Jonathan

Any chance of persuading you to ditch the old arith
packages in favour of numeric_std? Pretty please?

I do both and I believe it was your influence that started
me on numeric_std when I was having trouble with negative
numbers. There is something about numeric_std with something
simple, like +1, maybe, that's longer to write. Then if
you use signed and unsigned, then don't you write more to
send outputs to std_logic_vector outputs?

As Xilinx hangs on to the old package I worry superstitiously
about synthesis templates that create BRAMs. One time I
used both packages in the same module with no apparent
problem. Has any one mapped out all the conversions and
advantages of both libraries?