integer overflow in VHDL hey, Can someone help me why I get the following integer overflow error CODE: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity conv is port(sum: out std_logic_vector(28 downto 0) ); end conv; architecture behav of conv is signal s : integer range 0 to 31 := 31; begin -- behav sum <= conv_std_logic_vector((64-2**s) mod 2**29, 29); end behav; ERROR LOG: Error! integer overflow File: ./test1.vhd, line = 25, pos = 37 Scope: :$PROCESS_000 Time: 0 FS + 0 ./test1.vhd:25 sum <= conv_std_logic_vector((64-2**s) mod 2**29, 29); Set "intovf_severity_level" ncsim tcl variable to ignore this error. Type `help -variable intovf_severity_level` on ncsim> prompt. The maximum integer that can be used in VHDL is 2**31 -1 which mean that I can never used computations above that like for instance 2**31 itself? Any help is appreciated. Thanks

You pretty much answered why there's an overflow. The range of the 'integer' type is implementation dependant, but yes, it'll be 32 bits about everywhere (though that might be 64 bits nowadays with some tools?) This only means that you will have to go to signed (or unsigned), the size of these is up to you. (Yes they can be a bit harder to read but in this case, it should be obvious anyway): Code (Text): architecture behav of conv is constant v1 : signed(32 downto 0) := (31 => '1', others => '0'); constant diff : signed(32 downto 0) := to_signed(64,33) - v1; begin -- behav sum <= std_logic_vector(unsigned(diff(28 downto 0))); end behav; Hardcoded the v1 value to 2**31 for simplicity. I'm not sure whether this can be done well without adding contants, I got errors with signed'(31 => '1', others => '0') (I didn't have the ieee.std_logic_arith.all part, so I was missing conv_std_logic_vector; that's the only reason I replaced that)