and operator overloading

Discussion in 'VHDL' started by eladsolomon, Jun 4, 2016.

  1. eladsolomon

    eladsolomon

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    Jun 4, 2016
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    hi i have a question
    i need to make 2 integers do "and" and write them in the output.
    this is the code:

    Code (Text):
    library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.std_logic_unsigned.all ;


    package pack_std_logic_integers is
       function and (a,b :  integer  ) return std_logic_vector ;
    end pack_std_logic_integers;

    package body pack_std_logic_integers is

       function and (a,b :  integer ) return std_logic_vector is
          variable tempa : std_logic_vector(7 downto 0) ;
          variable tempb : std_logic_vector(7 downto 0) ;
          variable sum : std_logic_vector(7 downto 0) ;    
       begin
          tempa := a + "00000000";
          tempb := b + "00000000";
          sum := a and b;
          return sum;
       end and;

    end pack_std_logic_integers;

    use work.pack_std_logic_integers.all ;    
    library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.std_logic_unsigned.all ;

    entity tar11_4 is
     
       port ( a,b : integer range 0 to 255   ;
              dout   : out std_logic_vector(7 downto 0) );
    end tar11_4 ;
    architecture arc_tar11_4 of tar11_4 is
    begin
        dout <= a and b;
    end arc_tar11_3;

     
    now this is what i get from the compiler
    what should i do to make it work?
    please try to help me improve this code only with the library and packages we have here don't include any thing more.
    thanks.
     
    eladsolomon, Jun 4, 2016
    #1
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