Code owuld compile before, now doesnt recognise '='


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May 24, 2014
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hey all,

got a weird one, I had compiled all my designs as part of a MIPS processor at uni, they all compiled with nil errors. When I bought the designs home for simulation, for some reason I'm getting two errors that are boggling my mind

(note, i have not changed anything from when they compiled and tested fine at uni)

Error 1
can't determine definition of operator ""="" -- found 0 possible definitions

error 2
simplified sensitivity list is not supported by VHDL_1993, and is only supported for VHDL 2008

code samples

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:25:11 04/28/2009
-- Design Name:
-- Module Name: Dmem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


-- DO NOT MODIFY THE ENTITY DECLARATION
entity Dmem is
Port ( clk : in STD_LOGIC;
WE : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
WD : in STD_LOGIC_VECTOR (7 downto 0);
RD : out STD_LOGIC_VECTOR (7 downto 0));
end Dmem;

architecture Behavioral of Dmem is


-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector(7 downto 0);
type memory_t is array(255 downto 0) of word_t;

-- Declare the RAM signal.
signal ram : memory_t;

-- Register to hold the address
signal addr_reg : natural range 0 to 255;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(we = '1') then
ram(conv_integer(unsigned(A))) <= WD;
end if;

-- Register the address for reading
addr_reg <= conv_integer(unsigned(A));
end if;

end process;

RD <= ram(addr_reg);

end behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec3to8 is
Port ( wen: in std_logic_vector;
Wadd: in STD_LOGIC_Vector (2 downto 0);
wout: out STD_logic_vector (7 downto 0));
end dec3to8;

architecture Behavioral of dec3to8 is
-- Here go your declarations of new types and signals


begin
process(all) Begin
if (wen = '1') then
wout <= x"00";
Wout(conv_integer(unsigned(wadd))) <= '1';
else wout <= x"00";
end if;
end process;
end Behavioral;
 
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