multiple drivers problem,..please help

[bhatia.ankur8]

hello, i am designing a simple shift register. But getting an error:
Xst:528 - Multi-source in Unit <lab3d> on signal <led<7>>; this signal is connected to multiple drivers.

any help appreaciated. thankyou
the following is my vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab3d is
port (clk : in std_logic;
sw : in std_logic_vector(1 downto 0);
led : out std_logic_vector(7 downto 0));
end lab3d;

architecture Behavioral of lab3d is
signal s : std_logic_vector(7 downto 0);
signal temp : std_logic;
begin
s<= "10000000";
process(clk)
begin
if RISING_EDGE(clk) then
temp <= s(0);
for i in 0 to 6 loop
s(i+1) <= s(i);
end loop;
s(0) <= temp;
end if;
end process;
led <= s(7 downto 0);
end Behavioral;

 

[jeppe]

Try this

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lab3d is
        port (clk : in std_logic;
        sw : in std_logic_vector(1 downto 0);
       led : out std_logic_vector(7 downto 0));
end lab3d;

architecture Behavioral of lab3d is
       signal s : std_logic_vector(7 downto 0) :=  "10000000";
       signal temp : std_logic;
begin
       ------ Properly the problem  s<= "10000000";
  process(clk)
  begin
     if RISING_EDGE(clk) then
          temp <= s(0);
          for i in 0 to 6 loop
              s(i+1) <= s(i);
         end loop;
         s(0) <= temp;
     end if;
   end process;

   led <= s(7 downto 0);
end Behavioral

;

 

[bhatia.ankur8]

thankyou so much jeppe...its works now....