verilog, rtl, simulation

Discussion in 'VHDL' started by akshata@94, Apr 22, 2017.

  1. akshata@94

    akshata@94

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    hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values
     

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    akshata@94, Apr 22, 2017
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