Hi All, I have few questions in verilog. please can someone here help me understand this. Let's say, db_count = debounce_cnt at 10th positive edge. will "IF" condition in second always block be true at 10th positive edge? or will "IF" condition in second always block be true at 11th positive edge? but on 11th positive edge db_count will be set to 0 by first always block.. what is order of operation between "IF" and "Case" ? Though everything is in one always block and non blocking statements are used, "IF" and "Case" are two seperate blocks in themselves. Is the non-blocking behaviour of statements not confined seperately to "IF" and "Case" blocks? i.e. statements inside "IF" are non-blocking but are they non-blocking to statements inside "case" and vice versa? Code: `timescale 1 ns / 1 ns module debounce ( //inputs // what value is stored in pbtn_in and switch_in input clk, // clock input [3:0] pbtn_in, // pushbutton inputs input [7:0] switch_in, // slider switch inputs //outputs output reg [3:0] pbtn_db = 3'h0, // debounced outputs of pushbuttons output reg [7:0] swtch_db = 8'h0 // debounced outputs of slider switches ); parameter simulate = 0; // these are two ways to simulate. // simulate is a parameter. // what is the difference in two waits. localparam debounce_cnt = simulate ? 22'd5 // debounce clockwhen simulating : 22'd4_000_000; // debounce count when running on HW //shift registers used to debounce switches and buttons reg [21:0] db_count = 22'h0; //counter for debouncer // 8 switches. // 5 buttons. reg [4:0] shift_pb0 = 5'h0, shift_pb1 = 5'h0, shift_pb2 = 5'h0, shift_pb3 = 5'h0, shift_pb4 = 5'h0; reg [3:0] shift_swtch0 = 4'h0, shift_swtch1 = 4'h0, shift_swtch2 = 4'h0, shift_swtch3 = 4'h0; reg [3:0] shift_swtch4 = 4'h0, shift_swtch5 = 4'h0, shift_swtch6 = 4'h0, shift_swtch7 = 4'h0; // debounce clock // at positive edge, count is incremented always @(posedge clk) begin if (db_count == debounce_cnt) // it is 5 for simulation. db_count <= 1'b0; //takes 40mS to reach 4,000,000 else db_count <= db_count + 1'b1; end always @(posedge clk) begin // if this always and one is line 51 race condition. // if 51 runs first, then db_count will be set to szero when below condition is true. if (db_count == debounce_cnt) begin //sample every 40mS //shift registers for pushbuttons // i am shifting left once and doing a bitwise OR it with 0th bit of pbth_in // why // what is the value in pbtn_in shift_pb0 <= (shift_pb0 << 1) | pbtn_in[0]; shift_pb1 <= (shift_pb1 << 1) | pbtn_in[1]; shift_pb2 <= (shift_pb2 << 1) | pbtn_in[2]; shift_pb3 <= (shift_pb3 << 1) | pbtn_in[3]; shift_pb4 <= (shift_pb4 << 1) | pbtn_in[4]; //shift registers for slider switches // i am doing same operation here. // all these happen at same time. // what is the value in switch_in shift_swtch0 <= (shift_swtch0 << 1) | switch_in[0]; shift_swtch1 <= (shift_swtch1 << 1) | switch_in[1]; shift_swtch2 <= (shift_swtch2 << 1) | switch_in[2]; shift_swtch3 <= (shift_swtch3 << 1) | switch_in[3]; shift_swtch4 <= (shift_swtch4 << 1) | switch_in[4]; shift_swtch5 <= (shift_swtch5 << 1) | switch_in[5]; shift_swtch6 <= (shift_swtch6 << 1) | switch_in[6]; shift_swtch7 <= (shift_swtch7 << 1) | switch_in[7]; end //debounced pushbutton outputs // if first four bits are zero then bit zero is set to 0 // if first four bits are one then bit zero is set to 1 case(shift_pb0) 4'b0000: pbtn_db[0] <= 0; 4'b1111: pbtn_db[0] <= 1; endcase case(shift_pb1) 4'b0000: pbtn_db[1] <= 0; 4'b1111: pbtn_db[1] <= 1; endcase case(shift_pb2) 4'b0000: pbtn_db[2] <= 0; 4'b1111: pbtn_db[2] <= 1; endcase case(shift_pb3) 4'b0000: pbtn_db[3] <= 0; 4'b1111: pbtn_db[3] <= 1; endcase case(shift_pb4) 4'b0000: pbtn_db[4] <= 0; 4'b1111: pbtn_db[4] <= 1; endcase //debounced slider switch outputs case(shift_swtch0) 4'b0000: swtch_db[0] <= 0; 4'b1111: swtch_db[0] <= 1; endcase case(shift_swtch1) 4'b0000: swtch_db[1] <= 0; 4'b1111: swtch_db[1] <= 1; endcase case(shift_swtch2) 4'b0000: swtch_db[2] <= 0; 4'b1111: swtch_db[2] <= 1; endcase case(shift_swtch3) 4'b0000: swtch_db[3] <= 0; 4'b1111: swtch_db[3] <= 1; endcase case(shift_swtch4) 4'b0000: swtch_db[4] <= 0; 4'b1111: swtch_db[4] <= 1; endcase case(shift_swtch5) 4'b0000: swtch_db[5] <= 0; 4'b1111: swtch_db[5] <= 1; endcase case(shift_swtch6) 4'b0000: swtch_db[6] <= 0; 4'b1111: swtch_db[6] <= 1; endcase case(shift_swtch7) 4'b0000: swtch_db[7] <= 0; 4'b1111: swtch_db[7] <= 1; endcase end // if and case happen in parallel as it is non blocking statement. right. // for simulation i am not waiting for as much as i am waiting for synthesis. endmodule

Not trying to be a jerk, but have you considered asking in a Verilog group? This is a VHDL group. I'm just sayin'... Tell you what, I've cross posted it for you. Rick