VHDL -> 16-bit register with parallel load / shift_R / shift_L / asyncr_reset

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Hello everybody.
I want to write code for a 16-bit register with parallel load / shift_R / shift_L / asynchronous_reset.
I have already written the code(below) ,but I have no idea if it's correct.I want your help !!!
Code:
Screenshot from 2020-08-27 18-13-55.png
 
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If you want a 16-bit register that can load in parallel and also shift left/right with an async reset, you can do it in a simple process with a case or if block. I’ve seen people overcomplicate this, but it’s pretty straightforward once you break it down.
Sth like this should work for you:

process(clk, reset)
begin
if reset = '1' then
reg <= (others => '0'); -- async reset
elsif rising_edge(clk) then
case shift_control is
when "00" => -- no shift, just load
if load = '1' then
reg <= data_in; -- parallel load
end if;
when "01" => -- shift right
reg <= reg(0) & reg(15 downto 1); -- shift right
when "10" => -- shift left
reg <= reg(14 downto 0) & reg(15); -- shift left
when others =>
reg <= reg; -- hold current value
end case;
end if;
end process;

Just make sure you have the reset correctly, and for the shift logic, make sure you're shifting the right way (left or right) and not messing up the bits.
 

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