Shift left register using VHDL shift operator : sll trouble

Discussion in 'VHDL' started by Anviori, Apr 13, 2016.

  1. Anviori

    Anviori

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    I've implemented a shift left register with serial input and parallel output using a "slice" to implement the shift; but I can't figure out how to implement the same logic using an overloaded shift operator: 'sll' (shift left logical) operator. Thank you all for any help you can offer.

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;

    entity shift_reg is
    port(
    d :instd_logic;
    clk :instd_logic;
    rst_bar :instd_logic;
    q : out std_logic_vector(7downto0));
    end shift_reg;

    architecture post_vhdl_08 of shift_reg isbegin

    process(clk, rst_bar)

    variable q_int :std_logic_vector(7downto0);

    begin
    if rst_bar ='0'then
    q_int :=(others=>'0');elsif rising_edge(clk)then
    q_int := q_int(6downto0)& d;
    end if;

    q <= q_int;

    end process;

    end post_vhdl_08;
     
    Anviori, Apr 13, 2016
    #1
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