I'm just getting started with FPGAs and VHDL. I prefer the strong typing of VHDL over Verilog. For a particular device, how can I directly specify internal block configurations instead of allowing the system to determine those from high level programming constructs, and then allow the system to determine chip level block interconnects based on my block level i/o connection list? I realize that for most designs this is usually not the optimal design approach. Thanks in advance for any help.