Call for Papers - IEEE ISQED07




ISQED 2007

8th International Symposium & Exhibits on


March 26-28, 2007. San Jose, CA, USA

Leading Design for Quality & ManufacturabilityT

Paper Submission Deadline: September 30, 2006
Acceptance Notifications: November 23, 2006
Final Camera-Ready paper: January 3, 2007


ISQED is the pioneer and leading international conference dealing with the
design for manufacturability and quality issues front-to-back. ISQED spans
three days, Monday through Wednesday, in three parallel tracks, hosting near
100 technical presentations, six keynote speakers, two-three panel
discussions, workshops /tutorials and other informal meetings. Conference
proceedings are published by IEEE and hosted in the digital library.
Proceedings CD ROMs are published by ACM. In addition, continuing the
tradition of reaching a wider readership in the IC design community, ISQED
will continue to publish special issues in leading journals. The authors of
high quality papers will be invited to submit an extended version of their
papers for the special journal issues.

Papers are requested in the following areas:

A pioneer and leading multidisciplinary conference, ISQED accepts and
promotes papers related to the manufacturing, VLSI design and EDA. Authors
are invited to submit papers in the various disciplines of high level
design, circuit design, test & verification, design automation tools;
processes; flows, device modeling, semiconductor technology, and advance

1. Manufacturing, Semiconductor Process and Devices
1.1 Design for Manufacturability/Yield & Quality (DFM/DFY/DFQ)
1.2 Effects of Technology on IC Design, Performance, Reliability,
and Yield (TRD)

2. Design
2.1 System-level Design, Methodologies & Tools (SDM)
2.2 Package - Design Interactions & Co-Design (PDI)
2.3 Robust & Power-conscious Devices, Interconnects, and Circuits

2.4 Emerging/Innovative Process & Device Technologies and Design
Issues (EDT)

2.5 Design of Reliable Circuits and Systems (DFR)

3.1 EDA Methodologies, Tools, Flows & IP Cores; Interoperability
and Reuse (EDA)
3.2 Design Verification and Design for Testability (DVFT)
3.3 Physical Design, Methodologies & Tools (PDM)

The details of various topics of paper submission is as follows:

Design for Manufacturability/Yield & Quality (DFM/DFY/DFQ)

DFM/DFY/DFQ definitions, methodologies, matrices, and standards.
Quality-based design methodologies and flows for custom, semi-custom, ASIC,
FPGA, RF, memory, networking circuit, etc. Design flows and methodologies
for SoC, and SiP. Analysis, modeling, and abstraction of manufacturing
process parameters and effects for highly predictable silicon performance.
Design and synthesis of ICs considering factors such as: signal integrity,
transmission line effects, OPC, phase shifting, and sub-wavelength
lithography, manufacturing yield and technology capability. Design for
diagnosability, defect detection and tolerance; self-diagnosis,
calibration and repair. Design and manufacturabilty issues for Digital,
analog, mixed signal, RF, MEMS, opto-electronic, biochemical-electronic, and
nanotechnology based ICs. Redundency and other yield improving techniques.
Global, social, and economic implications of design quality.

Physical Design, Methodologies & Tools (PDM)

Physical design for manufacturing; Physical synthesis flows for
correct-by-construction quality silicon, implementation of large SoC
designs. Tool frameworks and data-models for tightly integrated incremental
synthesis, placement, routing, timing analysis and verification. Placement,
optimization, and routing techniques for noise sensitivity reduction and
fixing. Algorithms and flows for harnessing crosstalk-delay during physical
synthesis. Tool flows and techniques for antenna rule and electromigration
rule avoidance and fixing. Spare-cell strategies for ECO, decoupling
capacitance and antenna rule fixing. Physical planning tools for
predictable power-aware circuits. Reliable clock tree generation and clock
distribution methodologies for Gigahertz designs. EDA tools, design
techniques, and methodologies, dealing with issues such as: timing closure,
R, L, C extraction, ground/Vdd bounce, signal noise/cross-talk /substrate
noise, voltage drop, power rail integrity, electromigration, hot carriers,
EOS/ESD, plasma induced damage and other yield limiting effects, high
frequency effects, thermal effects, power estimation, EMI/EMC, proximity
correction & phase shift methods, verification (layout, circuit, function,

Design Verification and Design for Testability (DVFT)

Hardware and Software, Formal and simulation based design verification
techniques to ensure the functional correctness of hardware early in the
design cycle. DFT and BIST for digital and SoC. DFT for analog/mixed-signal
ICs and systems-on-chip, DFT/BIST for memories. Test synthesis and
synthesis for testability. DFT economics, DFT case studies. DFT and ATE.
Fault diagnosis, IDDQ test, novel test methods, effectiveness of test
methods, fault models and ATPG, and DPPM prediction. SoC/IP testing
strategies. Design methodologies dealing with the link between testability
and manufacturing.

EDA Methodologies, Tools, Flows & IP Cores; Interoperability and Reuse

EDA tools addressing design for manufacturing, yield, and reliability.
Management of design process, design flows and design databases. EDA tools
interoperability issues and implications. Effect of emerging technologies,
processes & devices on design flows, tools, and tool interoperability.
Emerging EDA standards. EDA design methodologies and tools that address
issues which impact the quality of the realization of designs into physical
integrated circuits. IP modeling and abstraction. Design and maintenance of
technology independent hard and soft IP blocks. Methods and tools for
analysis, comparison and qualification of libraries and hard IP blocks.
Challenges and solutions of the integration, testing, qualifying, and
manufacturing of IP blocks from multiple vendors. Third party testing of IP
blocks. Risk management of IP reuse. IP authoring tools and methodologies.

Robust & Power-conscious Devices, Interconnects, and Circuits (RDIC)

Device, substrate, interconnect, circuit , and IP block modeling and
simulation techniques; CMOS, Bipolar, and SiGe HBTs device modeling in the
context of advanced digital, RF and high-speed circuits. Modeling and
simulation of novel device and interconnect concepts. Signal integrity
analysis: coupling, inductive and charge sharing noise; noise avoidance
techniques. Modeling statistical process variations to improve design margin
and robustness, use of statistical circuit simulators. Power grid design,
analysis and optimization; timing analysis and optimization; thermal
analysis and design techniques for thermal management. Power-conscious
design methodologies and tools; low power devices, circuits and systems;
power-aware computing and communication; system-level power optimization
and management. Design techniques for leakage current management. Design of
robust 3D Integrated Circuits. Successful applications of TCAD to circuit
design. Impacts of process technologies on circuit design and capabilities
(e.g. low-Vt transistors versus increased off-state leakages) and the
accuracy, use and implementation of SPICE models that faithfully reflect
process technologies.

Emerging/Innovative Process & Device Technologies and Design Issues (EDT)

Emerging processes & device technologies and implications on IC design with
respect to design's time to market, yield, reliability, and quality.
Emerging issues in DSM CMOS: e.g. sub-threshold leakage, gate leakage,
technology road mapping and technology extrapolation techniques. New and
novel technologies such as SOI, Double-Gate (DG)-MOSFET, Gate-All-Around
(GAA)-MOSFET, Vertical-MOSFET, strained CMOS, high-bandwidth metallization,
3D integrated circuits, nanodevices, etc.

Package - Design Interactions & Co-Design (PDI)

Concurrent circuit, package, and PCB/PWB design and effect on quality. EDA
tools and methodologies dealing with the IC Packaging electrical and thermal
modeling and simulation for improved quality of product. SoC versus system
in a package (SiP): design and technology solutions and tradeoffs; MCM,
BGA, Flip Chip, and other innovative packaging techniques for various
applications such as mixed-signal and RFIC.

Design of Reliable Circuits and Systems (DFR)

Device and process reliability issues and effect on design of reliable
circuits and systems. ESD design for digital, mixed signal and RF
applications. Exploration of critical factors such as noise, substrate
coupling, cross-talk and power supply noise. Significance and trends in
process reliability effects such as gate oxide integrity, electromigration,
ESD, etc., and their relation to electronic design.

System-level Design, Methodologies & Tools (SDM)

Emerging system-level design paradigms, methods and tools aiming at quality.
System-level design process and flow management. System-level design
modeling, analysis and synthesis, estimation and verification for correct
high-quality hardware/software systems. Responsive, secure, and defect
tolerant systems. New concepts, methods and tools addressing system-level
design complexity and multitude of aspects. Methods and tools addressing the
usage of technology information and manufacturing feedback in the system-,
RTL- and logic level design. The influence of the nanometer technologies'
(application-dependent) yield and other issues on the system-, RTL- and
logic-level design. System-level trade-off analysis and multi-objective
(yield, power, delay, area .) optimization. Effective and efficient design,
implementation, analysis and validation of large SoCs integrating IP blocks
from multiple vendors. Global, Social, and Economical Implications of
Electronic System and Design Quality. Emerging standards and regulations
influencing system quality.

Submission of Papers
Paper submission must be done on-line via the conference web site at Authors should submit FULL-LENGTH, original, unpublished
papers (Minimum 4, maximum 6 pages) along with an abstract of about 200
words. Please check the as-printed appearance of your paper before
uploading. To permit a blind review, do not include name(s) or
affiliation(s) of the author(s) on the manuscript and abstract. The
complete contact author information needs to be entered separately. When
ready to submit your paper have the following information ready:

I Title of the paper
II Name, affiliation, complete mailing address and phone, fax, and
email of the first author
III Name, affiliations, city, state, country of additional authors
IV Person to whom correspondence should be sent, if other than the 1st
V Suggested area (as listed above)

The guidelines for the final paper format are provided on the conference web
site at Authors of the submitted papers must register and
attend the conference for their paper to be published.

Please note the following important dates:

Paper Submission Deadline: September 30, 2006
Acceptance Notifications: November 23, 2006
Final Camera-Ready paper: January 3, 2007

The International Symposium on Quality Electronic Design (ISQED), is a
premier Design & Design Automation conference, aimed at bridging the gap
between and integration of, electronic design tools and processes,
integrated circuit technologies, processes & manufacturing, to achieve
design quality. ISQED is the pioneer and leading conference dealing with
design for manufacturability and quality issues front-to-back. The
conference provides a forum to present and exchange ideas and to promote the
research, development, and application of design techniques & methods,
design processes, and EDA design methodologies and tools that address issues
which impact the quality of the realization of designs into physical
integrated circuits. The conference attendees are primarily designers of the
VLSI circuits & systems (IP & SoC), those involved in the research,
development, and application of EDA/CAD Tools & design flows, process/device
technologists, and semiconductor manufacturing specialists including
equipment vendors. ISQED emphasizes a holistic approach toward design
quality and intends to highlight and accelerate cooperation among the IC
Design, EDA, Semiconductor Process Technology and Manufacturing communities.

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