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VHDL
Can anyone think of a workaround - Ideally I want to pass an accesstype into an entity (not for synt
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[QUOTE="Andy, post: 4201035"] How about flattening your image into a single vector, and pass it in on an unconstrained array (e.g. SLV) port? Add generics (static) or other ports (dynamic) for pixel/row/column size to tell the model how to extract the image from the linear vector. Andy [/QUOTE]
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Can anyone think of a workaround - Ideally I want to pass an accesstype into an entity (not for synt
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