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Message: [QUOTE="Brian Drummond, post: 4201520"] My approach has been to perform binary I/O through an unofficial "portability layer". Modelsim and Xilinx ISIM (10.3) are the two I have experience of. ISIM insists on reading a short undocumented* header before the actual data. To satisfy this, I have simple scripts to separate header and file (using "head" and "tail) from ISIM output files, and to "cat" a header onto any binary file before I read it into ISIM. The other difference is endian-ness; I set a boolean flag ("is_isim") which controls end-swapping in both input/output routines. (* Xilinx refused to provide any documentation on the header despite a Webcase specifically asking for it) - Brian [/QUOTE]