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VHDL
Case choice must be a locally static expression
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[QUOTE="Peter, post: 4186634"] Hi, I have searched the net for the above mentioned warning from Modelsim, but I cant really understand whats the problem. I have declared some constants in a package: Constant MASKREG : unsigned(5 downto 0):= To_unsigned(0,6); Constant CONTREG : unsigned(5 downto 0):= To_unsigned(1,6); ...... They are used in a procedure in another entity: Procedure write_register is Begin case adr is when MASKREG => mask := shreg(mask'range); when CONTREG => cont := shreg(cont'range); when DEADTIMEREG => deadtime := shreg(deadtime'range); when FILTLOREG => filtlo := shreg(filtlo'range); when FILTHIREG => filthi := shreg(filthi'range); when MISCREG => misc := shreg(misc'range); when others => null; end case; End procedure write_register; Why is the case choice not considered locally static by Modelsim? Thanks in advance. /Peter [/QUOTE]
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Case choice must be a locally static expression
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