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VHDL
Case choice must be a locally static expression
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[QUOTE="HT-Lab, post: 4186810"] "Thomas Stanka" wrote in message With VHDL2008 you also no longer get the warning, I just created a quick test case based on Peter's code and with Modelsim I get: D:\Modelsim>vcom -2002 locally_static.vhd Model Technology ModelSim DE vcom 10.0 Compiler 2010.12 Dec 4 2010 -- Compiling entity x -- Compiling architecture rtl of x ** Warning: locally_static.vhd(18): Choice in CASE statement alternative must be locally static. D:\Modelsim>vcom -2008 locally_static.vhd Model Technology ModelSim DE vcom 10.0 Compiler 2010.12 Dec 4 2010 -- Compiling entity x -- Compiling architecture rtl of x Simple testcase shown below, Hans [URL="http://www.ht-lab.com"]www.ht-lab.com[/URL] library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity x is end x; architecture rtl of x is constant maskreg : unsigned(5 downto 0):= to_unsigned(0,6); signal shreg : unsigned(5 downto 0); procedure write_register(adr:in unsigned(5 downto 0)) is variable mask:unsigned(5 downto 0); begin case adr is when maskreg => mask := shreg(mask'range); -- Line18 when others => null; end case; end procedure write_register; begin end rtl; [/QUOTE]
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Case choice must be a locally static expression
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