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VHDL
Case choice must be a locally static expression
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[QUOTE="JimLewis, post: 4187343"] Hi Peter, This was addressed in the VHDL-2008 revision. There were a couple of changes to the language that now allow this to be locally static. Turn on the 2008 switch in modelsim. Double check that it works in your synthesis tool (or tools if you are making an FPGA then an ASIC) and you should be ok. Best, Jim [/QUOTE]
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Case choice must be a locally static expression
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