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Message: [QUOTE="Andy, post: 5128060"] If I'm not mistaken, if you explicitly define an initial value of 'Z' for each element of a signal at the signal's declaration, then all drivers associated with that signal take the same initial value as their default value (instead of the implicit 'U' for a signal with no explicit initialization inthe declaration). For an element of an inout port associated with such an initialized signal,which is really treated as an input-only element (and therefore never assigned), the element driver will retain the default value (e.g. 'Z') indefinitely. Meanwhile, other drivers (e.g. in other components) can explicitly override the 'Z' value, allowing them to treat the element as an "output", passing such values to the associated "inputs". Jim Lewis' (of Synthworks) Advanced Testbench course demonstrates this technique, but I have not tried it in synthesis yet. Andy [/QUOTE]