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VHDL
constants of sfixed in architecture body
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[QUOTE="Paul, post: 4099213"] Just a quick question: are you sure you want such large coefficients why is it better to use data types which divide by 18? I want to use Xilinx DSP48 slices on virtex4. My Coeffs have a width of 16bit (18 I could use). Input is 16bit also, multiplying get 32 bit, DSP48's adder has an input width of 48bit - there is room for sum results bigger than 1. I did scale my input to [1 1), my coeffs are [2 -2). Maybe I miss something? I did wonder why they have 18bits. BTW, my first implementation of fixed point arithmetic / FIR/IIR in FPGA :-) Thanks, Olaf [/QUOTE]
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constants of sfixed in architecture body
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