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VHDL
Easy type conversion question for you guys
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[QUOTE="Shannon, post: 2955680"] I have: Integer_variable: OUT INTEGER RANGE 0 TO 65535; and TYPE reg_type IS ARRAY (0 TO 12) OF STD_LOGIC_VECTOR(var1'RANGE); SIGNAL regs : reg_type; and what I want to accomplish is: Integer_variable <= to_integer(unsigned(regs(6) & regs(5) & regs(4) & regs(3))); Is there a way to accomplish this with just type casting? I'd rather not change the types assigned to 'Integer_variable and 'regs'. TYIA Shannon [/QUOTE]
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Easy type conversion question for you guys
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