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VHDL
Extracting type - Not possible or would it be useful in a future standard?
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[QUOTE="Tricky, post: 4127249"] I have just come across a situation where it might be beneficial to return the type of something so another type can be created. For example: I have this type defined in a package. type rec_t is record num : ufixed(7 downto 0); end record rec; type rec_array_t is array(integer range <>) of rec_t; then in a design file I want to create an array. The purpose of this array is simply to extract the "num" elements from a rec_array_t. At the moment I have to define: type local_array_t is array(integer range <>) of ufixed(rec_t.num'range); the problem comes when the "num" element is changed from a ufixed to a sfixed. I then have to manually redefine the local_array_t to cope with the type change. Am I overthinking a problem that might be worked around with a function (and by-passing the need for a local_array_t) or would this prove useful in the language? [/QUOTE]
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Extracting type - Not possible or would it be useful in a future standard?
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