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VHDL
Extracting type - Not possible or would it be useful in a future standard?
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[QUOTE="Paul Colin Gloster, post: 4130457"] Andy <jonesandy@comcast.net> sent on September 7th, 2010: |---------------------------------------| |"[..] | | | |[..] | |[..] (not sure why they limited 'base | |to use as a prefix in the first place).| | | |[..]" | |---------------------------------------| Not in the first place. 'Base can be liberally used in Ada. Regards, Paul Colin [/QUOTE]
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Extracting type - Not possible or would it be useful in a future standard?
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