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VHDL
Fixed Point Rounding
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[QUOTE="Tricky, post: 4073571"] Im using the new float fix lib, and Im getting a bit confused with the resize function. Im using the following code: video_us : out ufixed(7 downto 0) ... variable weighted_pix0 : ufixed(7 downto -12); variable weighted_pix1 : ufixed(7 downto -12); ....... video_us <= resize(weighted_pix0 + weighted_pix1, 7 , 0); Now, when the sum of the 2 weighted pixels is X.5, the rounded output (round style is defaulting to fixed_round) is always X, not X+1. Is there a rule Im missing? Is this not what the resize function is for, because otherwise whats the point of the "round_style" and "overflow_style" function arguments? do I have to go back to old way of rounding that is +0.5 and then truncating? Thanks for help in advance [/QUOTE]
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