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VHDL
Fixed Point Rounding
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[QUOTE="KJ, post: 4073919"] Should've said "I *have* used +0.5...". I've also used 'fixed_round'. Depending on the application though, this additional error for certain input combinations might still be acceptable. "+0.5 and truncate" is generally intermediate between 'fixed_truncate' and 'fixed_round' both in error and logic resources to implement. Which of the three methods is 'best' will depend on the accuracy requirements of the particular application. "+0.5 and truncate" is a design tradeoff that should be evaluated versus 'fixed_truncate' and 'fixed_round'...it's just another tool in the toolbox. As an example of resource usage, I took Tricky's code (actual code posted below) and ran it through Quartus 9.0 to produce the following results: Rounding method Logic resources =============== =============== fixed_round 44 +.5_and_trunc 39 fixed_truncate 29 Kevin Jennings --- START OF CODE library ieee_proposed; use ieee_proposed.math_utility_pkg.all; use ieee_proposed.fixed_pkg.all; entity Resizer_Adder is port( weighted_pix0: in ufixed(7 downto -12); weighted_pix1: in ufixed(7 downto -12); video_us: out ufixed(7 downto 0)); end Resizer_Adder; architecture rtl of Resizer_Adder is begin -- Uncomment the line you would like to evaluate video_us <= resize(weighted_pix0 + weighted_pix1, 7 , 0, fixed_overflow_style,fixed_round); -- video_us <= resize(weighted_pix0 + weighted_pix1 + to_ufixed(0.5,-1,-1), 7 , 0, fixed_overflow_style,fixed_truncate); -- video_us <= resize(weighted_pix0 + weighted_pix1, 7 , 0, fixed_overflow_style,fixed_truncate); end rtl; --- END OF CODE [/QUOTE]
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