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VHDL
Fixed Point Rounding
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[QUOTE="Tricky, post: 4075039"] For me, data forking (if I understand correctly - is that like compounding errors?) shouldnt be an issue becuase this is the final output. The 12 bits are carried only because I have a previous divide (by a constant 2^n, with n as a generic) with input data only carrying 4 bits fractional. 12 bits contains the worst possible case of N, with me expecting the synthesiser to clear up anything thats overkill. And actually, for my output, I require X.5 to always round to X+1, so there is no error. [/QUOTE]
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